Enum efm32gg11b::vdac0::ch0ctrl::TRIGMODE_A [−][src]
#[repr(u8)] pub enum TRIGMODE_A { SW, PRS, REFRESH, SWPRS, SWREFRESH, LESENSE, }
Expand description
Channel 0 Trigger Mode
Value on reset: 0
Variants
0: Channel 0 is triggered by CH0DATA or COMBDATA write
1: Channel 0 is triggered by PRS input
2: Channel 0 is triggered by Refresh timer
3: Channel 0 is triggered by CH0DATA/COMBDATA write or PRS input
4: Channel 0 is triggered by CH0DATA/COMBDATA write or Refresh timer
5: Channel 0 is triggered by LESENSE
Trait Implementations
Performs the conversion.