Struct efm32gg11b::prs::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub swpulse: SWPULSE,
    pub swlevel: SWLEVEL,
    pub routepen: ROUTEPEN,
    pub routeloc0: ROUTELOC0,
    pub routeloc1: ROUTELOC1,
    pub routeloc2: ROUTELOC2,
    pub routeloc3: ROUTELOC3,
    pub routeloc4: ROUTELOC4,
    pub routeloc5: ROUTELOC5,
    pub ctrl: CTRL,
    pub dmareq0: DMAREQ0,
    pub dmareq1: DMAREQ1,
    pub peek: PEEK,
    pub ch0_ctrl: CH0_CTRL,
    pub ch1_ctrl: CH1_CTRL,
    pub ch2_ctrl: CH2_CTRL,
    pub ch3_ctrl: CH3_CTRL,
    pub ch4_ctrl: CH4_CTRL,
    pub ch5_ctrl: CH5_CTRL,
    pub ch6_ctrl: CH6_CTRL,
    pub ch7_ctrl: CH7_CTRL,
    pub ch8_ctrl: CH8_CTRL,
    pub ch9_ctrl: CH9_CTRL,
    pub ch10_ctrl: CH10_CTRL,
    pub ch11_ctrl: CH11_CTRL,
    pub ch12_ctrl: CH12_CTRL,
    pub ch13_ctrl: CH13_CTRL,
    pub ch14_ctrl: CH14_CTRL,
    pub ch15_ctrl: CH15_CTRL,
    pub ch16_ctrl: CH16_CTRL,
    pub ch17_ctrl: CH17_CTRL,
    pub ch18_ctrl: CH18_CTRL,
    pub ch19_ctrl: CH19_CTRL,
    pub ch20_ctrl: CH20_CTRL,
    pub ch21_ctrl: CH21_CTRL,
    pub ch22_ctrl: CH22_CTRL,
    pub ch23_ctrl: CH23_CTRL,
    // some fields omitted
}

Register block

Fields

swpulse: SWPULSE

0x00 - Software Pulse Register

swlevel: SWLEVEL

0x04 - Software Level Register

routepen: ROUTEPEN

0x08 - I/O Routing Pin Enable Register

routeloc0: ROUTELOC0

0x10 - I/O Routing Location Register

routeloc1: ROUTELOC1

0x14 - I/O Routing Location Register

routeloc2: ROUTELOC2

0x18 - I/O Routing Location Register

routeloc3: ROUTELOC3

0x1c - I/O Routing Location Register

routeloc4: ROUTELOC4

0x20 - I/O Routing Location Register

routeloc5: ROUTELOC5

0x24 - I/O Routing Location Register

ctrl: CTRL

0x30 - Control Register

dmareq0: DMAREQ0

0x34 - DMA Request 0 Register

dmareq1: DMAREQ1

0x38 - DMA Request 1 Register

peek: PEEK

0x40 - PRS Channel Values

ch0_ctrl: CH0_CTRL

0x50 - Channel Control Register

ch1_ctrl: CH1_CTRL

0x54 - Channel Control Register

ch2_ctrl: CH2_CTRL

0x58 - Channel Control Register

ch3_ctrl: CH3_CTRL

0x5c - Channel Control Register

ch4_ctrl: CH4_CTRL

0x60 - Channel Control Register

ch5_ctrl: CH5_CTRL

0x64 - Channel Control Register

ch6_ctrl: CH6_CTRL

0x68 - Channel Control Register

ch7_ctrl: CH7_CTRL

0x6c - Channel Control Register

ch8_ctrl: CH8_CTRL

0x70 - Channel Control Register

ch9_ctrl: CH9_CTRL

0x74 - Channel Control Register

ch10_ctrl: CH10_CTRL

0x78 - Channel Control Register

ch11_ctrl: CH11_CTRL

0x7c - Channel Control Register

ch12_ctrl: CH12_CTRL

0x80 - Channel Control Register

ch13_ctrl: CH13_CTRL

0x84 - Channel Control Register

ch14_ctrl: CH14_CTRL

0x88 - Channel Control Register

ch15_ctrl: CH15_CTRL

0x8c - Channel Control Register

ch16_ctrl: CH16_CTRL

0x90 - Channel Control Register

ch17_ctrl: CH17_CTRL

0x94 - Channel Control Register

ch18_ctrl: CH18_CTRL

0x98 - Channel Control Register

ch19_ctrl: CH19_CTRL

0x9c - Channel Control Register

ch20_ctrl: CH20_CTRL

0xa0 - Channel Control Register

ch21_ctrl: CH21_CTRL

0xa4 - Channel Control Register

ch22_ctrl: CH22_CTRL

0xa8 - Channel Control Register

ch23_ctrl: CH23_CTRL

0xac - Channel Control Register