Enum efm32gg11b::msc::cacheconfig0::CACHELPLEVEL_A [−][src]
#[repr(u8)] pub enum CACHELPLEVEL_A { BASE, ADVANCED, MINACTIVITY, }
Expand description
Instruction Cache Low-Power Level
Value on reset: 3
Variants
0: Base instruction cache functionality.
1: Advanced buffering mode, where the cache uses the fetch pattern to predict highly accessed data and store it in low-energy memory.
3: Minimum activity mode, which allows the cache to minimize activity in logic that it predicts has a low probability being used. This mode can introduce wait-states into the instruction fetch stream when the cache exits one of its low-activity states. The number of wait-states introduced is small, but users running with 0-wait-state memory and wishing to reduce the variability that the cache might introduce with additional wait-states may wish to lower the cache low-power level. Note, this mode includes the advanced buffering mode functionality.
Trait Implementations
Performs the conversion.