Struct efm32gg11b::ldma::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {}Show fields
pub ctrl: CTRL, pub status: STATUS, pub sync: SYNC, pub chen: CHEN, pub chbusy: CHBUSY, pub chdone: CHDONE, pub dbghalt: DBGHALT, pub swreq: SWREQ, pub reqdis: REQDIS, pub reqpend: REQPEND, pub linkload: LINKLOAD, pub reqclear: REQCLEAR, pub if_: IF, pub ifs: IFS, pub ifc: IFC, pub ien: IEN, pub ch0_reqsel: CH0_REQSEL, pub ch0_cfg: CH0_CFG, pub ch0_loop: CH0_LOOP, pub ch0_ctrl: CH0_CTRL, pub ch0_src: CH0_SRC, pub ch0_dst: CH0_DST, pub ch0_link: CH0_LINK, pub ch1_reqsel: CH1_REQSEL, pub ch1_cfg: CH1_CFG, pub ch1_loop: CH1_LOOP, pub ch1_ctrl: CH1_CTRL, pub ch1_src: CH1_SRC, pub ch1_dst: CH1_DST, pub ch1_link: CH1_LINK, pub ch2_reqsel: CH2_REQSEL, pub ch2_cfg: CH2_CFG, pub ch2_loop: CH2_LOOP, pub ch2_ctrl: CH2_CTRL, pub ch2_src: CH2_SRC, pub ch2_dst: CH2_DST, pub ch2_link: CH2_LINK, pub ch3_reqsel: CH3_REQSEL, pub ch3_cfg: CH3_CFG, pub ch3_loop: CH3_LOOP, pub ch3_ctrl: CH3_CTRL, pub ch3_src: CH3_SRC, pub ch3_dst: CH3_DST, pub ch3_link: CH3_LINK, pub ch4_reqsel: CH4_REQSEL, pub ch4_cfg: CH4_CFG, pub ch4_loop: CH4_LOOP, pub ch4_ctrl: CH4_CTRL, pub ch4_src: CH4_SRC, pub ch4_dst: CH4_DST, pub ch4_link: CH4_LINK, pub ch5_reqsel: CH5_REQSEL, pub ch5_cfg: CH5_CFG, pub ch5_loop: CH5_LOOP, pub ch5_ctrl: CH5_CTRL, pub ch5_src: CH5_SRC, pub ch5_dst: CH5_DST, pub ch5_link: CH5_LINK, pub ch6_reqsel: CH6_REQSEL, pub ch6_cfg: CH6_CFG, pub ch6_loop: CH6_LOOP, pub ch6_ctrl: CH6_CTRL, pub ch6_src: CH6_SRC, pub ch6_dst: CH6_DST, pub ch6_link: CH6_LINK, pub ch7_reqsel: CH7_REQSEL, pub ch7_cfg: CH7_CFG, pub ch7_loop: CH7_LOOP, pub ch7_ctrl: CH7_CTRL, pub ch7_src: CH7_SRC, pub ch7_dst: CH7_DST, pub ch7_link: CH7_LINK, pub ch8_reqsel: CH8_REQSEL, pub ch8_cfg: CH8_CFG, pub ch8_loop: CH8_LOOP, pub ch8_ctrl: CH8_CTRL, pub ch8_src: CH8_SRC, pub ch8_dst: CH8_DST, pub ch8_link: CH8_LINK, pub ch9_reqsel: CH9_REQSEL, pub ch9_cfg: CH9_CFG, pub ch9_loop: CH9_LOOP, pub ch9_ctrl: CH9_CTRL, pub ch9_src: CH9_SRC, pub ch9_dst: CH9_DST, pub ch9_link: CH9_LINK, pub ch10_reqsel: CH10_REQSEL, pub ch10_cfg: CH10_CFG, pub ch10_loop: CH10_LOOP, pub ch10_ctrl: CH10_CTRL, pub ch10_src: CH10_SRC, pub ch10_dst: CH10_DST, pub ch10_link: CH10_LINK, pub ch11_reqsel: CH11_REQSEL, pub ch11_cfg: CH11_CFG, pub ch11_loop: CH11_LOOP, pub ch11_ctrl: CH11_CTRL, pub ch11_src: CH11_SRC, pub ch11_dst: CH11_DST, pub ch11_link: CH11_LINK, pub ch12_reqsel: CH12_REQSEL, pub ch12_cfg: CH12_CFG, pub ch12_loop: CH12_LOOP, pub ch12_ctrl: CH12_CTRL, pub ch12_src: CH12_SRC, pub ch12_dst: CH12_DST, pub ch12_link: CH12_LINK, pub ch13_reqsel: CH13_REQSEL, pub ch13_cfg: CH13_CFG, pub ch13_loop: CH13_LOOP, pub ch13_ctrl: CH13_CTRL, pub ch13_src: CH13_SRC, pub ch13_dst: CH13_DST, pub ch13_link: CH13_LINK, pub ch14_reqsel: CH14_REQSEL, pub ch14_cfg: CH14_CFG, pub ch14_loop: CH14_LOOP, pub ch14_ctrl: CH14_CTRL, pub ch14_src: CH14_SRC, pub ch14_dst: CH14_DST, pub ch14_link: CH14_LINK, pub ch15_reqsel: CH15_REQSEL, pub ch15_cfg: CH15_CFG, pub ch15_loop: CH15_LOOP, pub ch15_ctrl: CH15_CTRL, pub ch15_src: CH15_SRC, pub ch15_dst: CH15_DST, pub ch15_link: CH15_LINK, pub ch16_reqsel: CH16_REQSEL, pub ch16_cfg: CH16_CFG, pub ch16_loop: CH16_LOOP, pub ch16_ctrl: CH16_CTRL, pub ch16_src: CH16_SRC, pub ch16_dst: CH16_DST, pub ch16_link: CH16_LINK, pub ch17_reqsel: CH17_REQSEL, pub ch17_cfg: CH17_CFG, pub ch17_loop: CH17_LOOP, pub ch17_ctrl: CH17_CTRL, pub ch17_src: CH17_SRC, pub ch17_dst: CH17_DST, pub ch17_link: CH17_LINK, pub ch18_reqsel: CH18_REQSEL, pub ch18_cfg: CH18_CFG, pub ch18_loop: CH18_LOOP, pub ch18_ctrl: CH18_CTRL, pub ch18_src: CH18_SRC, pub ch18_dst: CH18_DST, pub ch18_link: CH18_LINK, pub ch19_reqsel: CH19_REQSEL, pub ch19_cfg: CH19_CFG, pub ch19_loop: CH19_LOOP, pub ch19_ctrl: CH19_CTRL, pub ch19_src: CH19_SRC, pub ch19_dst: CH19_DST, pub ch19_link: CH19_LINK, pub ch20_reqsel: CH20_REQSEL, pub ch20_cfg: CH20_CFG, pub ch20_loop: CH20_LOOP, pub ch20_ctrl: CH20_CTRL, pub ch20_src: CH20_SRC, pub ch20_dst: CH20_DST, pub ch20_link: CH20_LINK, pub ch21_reqsel: CH21_REQSEL, pub ch21_cfg: CH21_CFG, pub ch21_loop: CH21_LOOP, pub ch21_ctrl: CH21_CTRL, pub ch21_src: CH21_SRC, pub ch21_dst: CH21_DST, pub ch21_link: CH21_LINK, pub ch22_reqsel: CH22_REQSEL, pub ch22_cfg: CH22_CFG, pub ch22_loop: CH22_LOOP, pub ch22_ctrl: CH22_CTRL, pub ch22_src: CH22_SRC, pub ch22_dst: CH22_DST, pub ch22_link: CH22_LINK, pub ch23_reqsel: CH23_REQSEL, pub ch23_cfg: CH23_CFG, pub ch23_loop: CH23_LOOP, pub ch23_ctrl: CH23_CTRL, pub ch23_src: CH23_SRC, pub ch23_dst: CH23_DST, pub ch23_link: CH23_LINK, // some fields omitted
Expand description
Register block
Fields
ctrl: CTRL
0x00 - DMA Control Register
status: STATUS
0x04 - DMA Status Register
sync: SYNC
0x08 - DMA Synchronization Trigger Register (Single-Cycle RMW)
chen: CHEN
0x20 - DMA Channel Enable Register (Single-Cycle RMW)
chbusy: CHBUSY
0x24 - DMA Channel Busy Register
chdone: CHDONE
0x28 - DMA Channel Linking Done Register (Single-Cycle RMW)
dbghalt: DBGHALT
0x2c - DMA Channel Debug Halt Register
swreq: SWREQ
0x30 - DMA Channel Software Transfer Request Register
reqdis: REQDIS
0x34 - DMA Channel Request Disable Register
reqpend: REQPEND
0x38 - DMA Channel Requests Pending Register
linkload: LINKLOAD
0x3c - DMA Channel Link Load Register
reqclear: REQCLEAR
0x40 - DMA Channel Request Clear Register
if_: IF
0x60 - Interrupt Flag Register
ifs: IFS
0x64 - Interrupt Flag Set Register
ifc: IFC
0x68 - Interrupt Flag Clear Register
ien: IEN
0x6c - Interrupt Enable Register
ch0_reqsel: CH0_REQSEL
0x80 - Channel Peripheral Request Select Register
ch0_cfg: CH0_CFG
0x84 - Channel Configuration Register
ch0_loop: CH0_LOOP
0x88 - Channel Loop Counter Register
ch0_ctrl: CH0_CTRL
0x8c - Channel Descriptor Control Word Register
ch0_src: CH0_SRC
0x90 - Channel Descriptor Source Data Address Register
ch0_dst: CH0_DST
0x94 - Channel Descriptor Destination Data Address Register
ch0_link: CH0_LINK
0x98 - Channel Descriptor Link Structure Address Register
ch1_reqsel: CH1_REQSEL
0xb0 - Channel Peripheral Request Select Register
ch1_cfg: CH1_CFG
0xb4 - Channel Configuration Register
ch1_loop: CH1_LOOP
0xb8 - Channel Loop Counter Register
ch1_ctrl: CH1_CTRL
0xbc - Channel Descriptor Control Word Register
ch1_src: CH1_SRC
0xc0 - Channel Descriptor Source Data Address Register
ch1_dst: CH1_DST
0xc4 - Channel Descriptor Destination Data Address Register
ch1_link: CH1_LINK
0xc8 - Channel Descriptor Link Structure Address Register
ch2_reqsel: CH2_REQSEL
0xe0 - Channel Peripheral Request Select Register
ch2_cfg: CH2_CFG
0xe4 - Channel Configuration Register
ch2_loop: CH2_LOOP
0xe8 - Channel Loop Counter Register
ch2_ctrl: CH2_CTRL
0xec - Channel Descriptor Control Word Register
ch2_src: CH2_SRC
0xf0 - Channel Descriptor Source Data Address Register
ch2_dst: CH2_DST
0xf4 - Channel Descriptor Destination Data Address Register
ch2_link: CH2_LINK
0xf8 - Channel Descriptor Link Structure Address Register
ch3_reqsel: CH3_REQSEL
0x110 - Channel Peripheral Request Select Register
ch3_cfg: CH3_CFG
0x114 - Channel Configuration Register
ch3_loop: CH3_LOOP
0x118 - Channel Loop Counter Register
ch3_ctrl: CH3_CTRL
0x11c - Channel Descriptor Control Word Register
ch3_src: CH3_SRC
0x120 - Channel Descriptor Source Data Address Register
ch3_dst: CH3_DST
0x124 - Channel Descriptor Destination Data Address Register
ch3_link: CH3_LINK
0x128 - Channel Descriptor Link Structure Address Register
ch4_reqsel: CH4_REQSEL
0x140 - Channel Peripheral Request Select Register
ch4_cfg: CH4_CFG
0x144 - Channel Configuration Register
ch4_loop: CH4_LOOP
0x148 - Channel Loop Counter Register
ch4_ctrl: CH4_CTRL
0x14c - Channel Descriptor Control Word Register
ch4_src: CH4_SRC
0x150 - Channel Descriptor Source Data Address Register
ch4_dst: CH4_DST
0x154 - Channel Descriptor Destination Data Address Register
ch4_link: CH4_LINK
0x158 - Channel Descriptor Link Structure Address Register
ch5_reqsel: CH5_REQSEL
0x170 - Channel Peripheral Request Select Register
ch5_cfg: CH5_CFG
0x174 - Channel Configuration Register
ch5_loop: CH5_LOOP
0x178 - Channel Loop Counter Register
ch5_ctrl: CH5_CTRL
0x17c - Channel Descriptor Control Word Register
ch5_src: CH5_SRC
0x180 - Channel Descriptor Source Data Address Register
ch5_dst: CH5_DST
0x184 - Channel Descriptor Destination Data Address Register
ch5_link: CH5_LINK
0x188 - Channel Descriptor Link Structure Address Register
ch6_reqsel: CH6_REQSEL
0x1a0 - Channel Peripheral Request Select Register
ch6_cfg: CH6_CFG
0x1a4 - Channel Configuration Register
ch6_loop: CH6_LOOP
0x1a8 - Channel Loop Counter Register
ch6_ctrl: CH6_CTRL
0x1ac - Channel Descriptor Control Word Register
ch6_src: CH6_SRC
0x1b0 - Channel Descriptor Source Data Address Register
ch6_dst: CH6_DST
0x1b4 - Channel Descriptor Destination Data Address Register
ch6_link: CH6_LINK
0x1b8 - Channel Descriptor Link Structure Address Register
ch7_reqsel: CH7_REQSEL
0x1d0 - Channel Peripheral Request Select Register
ch7_cfg: CH7_CFG
0x1d4 - Channel Configuration Register
ch7_loop: CH7_LOOP
0x1d8 - Channel Loop Counter Register
ch7_ctrl: CH7_CTRL
0x1dc - Channel Descriptor Control Word Register
ch7_src: CH7_SRC
0x1e0 - Channel Descriptor Source Data Address Register
ch7_dst: CH7_DST
0x1e4 - Channel Descriptor Destination Data Address Register
ch7_link: CH7_LINK
0x1e8 - Channel Descriptor Link Structure Address Register
ch8_reqsel: CH8_REQSEL
0x200 - Channel Peripheral Request Select Register
ch8_cfg: CH8_CFG
0x204 - Channel Configuration Register
ch8_loop: CH8_LOOP
0x208 - Channel Loop Counter Register
ch8_ctrl: CH8_CTRL
0x20c - Channel Descriptor Control Word Register
ch8_src: CH8_SRC
0x210 - Channel Descriptor Source Data Address Register
ch8_dst: CH8_DST
0x214 - Channel Descriptor Destination Data Address Register
ch8_link: CH8_LINK
0x218 - Channel Descriptor Link Structure Address Register
ch9_reqsel: CH9_REQSEL
0x230 - Channel Peripheral Request Select Register
ch9_cfg: CH9_CFG
0x234 - Channel Configuration Register
ch9_loop: CH9_LOOP
0x238 - Channel Loop Counter Register
ch9_ctrl: CH9_CTRL
0x23c - Channel Descriptor Control Word Register
ch9_src: CH9_SRC
0x240 - Channel Descriptor Source Data Address Register
ch9_dst: CH9_DST
0x244 - Channel Descriptor Destination Data Address Register
ch9_link: CH9_LINK
0x248 - Channel Descriptor Link Structure Address Register
ch10_reqsel: CH10_REQSEL
0x260 - Channel Peripheral Request Select Register
ch10_cfg: CH10_CFG
0x264 - Channel Configuration Register
ch10_loop: CH10_LOOP
0x268 - Channel Loop Counter Register
ch10_ctrl: CH10_CTRL
0x26c - Channel Descriptor Control Word Register
ch10_src: CH10_SRC
0x270 - Channel Descriptor Source Data Address Register
ch10_dst: CH10_DST
0x274 - Channel Descriptor Destination Data Address Register
ch10_link: CH10_LINK
0x278 - Channel Descriptor Link Structure Address Register
ch11_reqsel: CH11_REQSEL
0x290 - Channel Peripheral Request Select Register
ch11_cfg: CH11_CFG
0x294 - Channel Configuration Register
ch11_loop: CH11_LOOP
0x298 - Channel Loop Counter Register
ch11_ctrl: CH11_CTRL
0x29c - Channel Descriptor Control Word Register
ch11_src: CH11_SRC
0x2a0 - Channel Descriptor Source Data Address Register
ch11_dst: CH11_DST
0x2a4 - Channel Descriptor Destination Data Address Register
ch11_link: CH11_LINK
0x2a8 - Channel Descriptor Link Structure Address Register
ch12_reqsel: CH12_REQSEL
0x2c0 - Channel Peripheral Request Select Register
ch12_cfg: CH12_CFG
0x2c4 - Channel Configuration Register
ch12_loop: CH12_LOOP
0x2c8 - Channel Loop Counter Register
ch12_ctrl: CH12_CTRL
0x2cc - Channel Descriptor Control Word Register
ch12_src: CH12_SRC
0x2d0 - Channel Descriptor Source Data Address Register
ch12_dst: CH12_DST
0x2d4 - Channel Descriptor Destination Data Address Register
ch12_link: CH12_LINK
0x2d8 - Channel Descriptor Link Structure Address Register
ch13_reqsel: CH13_REQSEL
0x2f0 - Channel Peripheral Request Select Register
ch13_cfg: CH13_CFG
0x2f4 - Channel Configuration Register
ch13_loop: CH13_LOOP
0x2f8 - Channel Loop Counter Register
ch13_ctrl: CH13_CTRL
0x2fc - Channel Descriptor Control Word Register
ch13_src: CH13_SRC
0x300 - Channel Descriptor Source Data Address Register
ch13_dst: CH13_DST
0x304 - Channel Descriptor Destination Data Address Register
ch13_link: CH13_LINK
0x308 - Channel Descriptor Link Structure Address Register
ch14_reqsel: CH14_REQSEL
0x320 - Channel Peripheral Request Select Register
ch14_cfg: CH14_CFG
0x324 - Channel Configuration Register
ch14_loop: CH14_LOOP
0x328 - Channel Loop Counter Register
ch14_ctrl: CH14_CTRL
0x32c - Channel Descriptor Control Word Register
ch14_src: CH14_SRC
0x330 - Channel Descriptor Source Data Address Register
ch14_dst: CH14_DST
0x334 - Channel Descriptor Destination Data Address Register
ch14_link: CH14_LINK
0x338 - Channel Descriptor Link Structure Address Register
ch15_reqsel: CH15_REQSEL
0x350 - Channel Peripheral Request Select Register
ch15_cfg: CH15_CFG
0x354 - Channel Configuration Register
ch15_loop: CH15_LOOP
0x358 - Channel Loop Counter Register
ch15_ctrl: CH15_CTRL
0x35c - Channel Descriptor Control Word Register
ch15_src: CH15_SRC
0x360 - Channel Descriptor Source Data Address Register
ch15_dst: CH15_DST
0x364 - Channel Descriptor Destination Data Address Register
ch15_link: CH15_LINK
0x368 - Channel Descriptor Link Structure Address Register
ch16_reqsel: CH16_REQSEL
0x380 - Channel Peripheral Request Select Register
ch16_cfg: CH16_CFG
0x384 - Channel Configuration Register
ch16_loop: CH16_LOOP
0x388 - Channel Loop Counter Register
ch16_ctrl: CH16_CTRL
0x38c - Channel Descriptor Control Word Register
ch16_src: CH16_SRC
0x390 - Channel Descriptor Source Data Address Register
ch16_dst: CH16_DST
0x394 - Channel Descriptor Destination Data Address Register
ch16_link: CH16_LINK
0x398 - Channel Descriptor Link Structure Address Register
ch17_reqsel: CH17_REQSEL
0x3b0 - Channel Peripheral Request Select Register
ch17_cfg: CH17_CFG
0x3b4 - Channel Configuration Register
ch17_loop: CH17_LOOP
0x3b8 - Channel Loop Counter Register
ch17_ctrl: CH17_CTRL
0x3bc - Channel Descriptor Control Word Register
ch17_src: CH17_SRC
0x3c0 - Channel Descriptor Source Data Address Register
ch17_dst: CH17_DST
0x3c4 - Channel Descriptor Destination Data Address Register
ch17_link: CH17_LINK
0x3c8 - Channel Descriptor Link Structure Address Register
ch18_reqsel: CH18_REQSEL
0x3e0 - Channel Peripheral Request Select Register
ch18_cfg: CH18_CFG
0x3e4 - Channel Configuration Register
ch18_loop: CH18_LOOP
0x3e8 - Channel Loop Counter Register
ch18_ctrl: CH18_CTRL
0x3ec - Channel Descriptor Control Word Register
ch18_src: CH18_SRC
0x3f0 - Channel Descriptor Source Data Address Register
ch18_dst: CH18_DST
0x3f4 - Channel Descriptor Destination Data Address Register
ch18_link: CH18_LINK
0x3f8 - Channel Descriptor Link Structure Address Register
ch19_reqsel: CH19_REQSEL
0x410 - Channel Peripheral Request Select Register
ch19_cfg: CH19_CFG
0x414 - Channel Configuration Register
ch19_loop: CH19_LOOP
0x418 - Channel Loop Counter Register
ch19_ctrl: CH19_CTRL
0x41c - Channel Descriptor Control Word Register
ch19_src: CH19_SRC
0x420 - Channel Descriptor Source Data Address Register
ch19_dst: CH19_DST
0x424 - Channel Descriptor Destination Data Address Register
ch19_link: CH19_LINK
0x428 - Channel Descriptor Link Structure Address Register
ch20_reqsel: CH20_REQSEL
0x440 - Channel Peripheral Request Select Register
ch20_cfg: CH20_CFG
0x444 - Channel Configuration Register
ch20_loop: CH20_LOOP
0x448 - Channel Loop Counter Register
ch20_ctrl: CH20_CTRL
0x44c - Channel Descriptor Control Word Register
ch20_src: CH20_SRC
0x450 - Channel Descriptor Source Data Address Register
ch20_dst: CH20_DST
0x454 - Channel Descriptor Destination Data Address Register
ch20_link: CH20_LINK
0x458 - Channel Descriptor Link Structure Address Register
ch21_reqsel: CH21_REQSEL
0x470 - Channel Peripheral Request Select Register
ch21_cfg: CH21_CFG
0x474 - Channel Configuration Register
ch21_loop: CH21_LOOP
0x478 - Channel Loop Counter Register
ch21_ctrl: CH21_CTRL
0x47c - Channel Descriptor Control Word Register
ch21_src: CH21_SRC
0x480 - Channel Descriptor Source Data Address Register
ch21_dst: CH21_DST
0x484 - Channel Descriptor Destination Data Address Register
ch21_link: CH21_LINK
0x488 - Channel Descriptor Link Structure Address Register
ch22_reqsel: CH22_REQSEL
0x4a0 - Channel Peripheral Request Select Register
ch22_cfg: CH22_CFG
0x4a4 - Channel Configuration Register
ch22_loop: CH22_LOOP
0x4a8 - Channel Loop Counter Register
ch22_ctrl: CH22_CTRL
0x4ac - Channel Descriptor Control Word Register
ch22_src: CH22_SRC
0x4b0 - Channel Descriptor Source Data Address Register
ch22_dst: CH22_DST
0x4b4 - Channel Descriptor Destination Data Address Register
ch22_link: CH22_LINK
0x4b8 - Channel Descriptor Link Structure Address Register
ch23_reqsel: CH23_REQSEL
0x4d0 - Channel Peripheral Request Select Register
ch23_cfg: CH23_CFG
0x4d4 - Channel Configuration Register
ch23_loop: CH23_LOOP
0x4d8 - Channel Loop Counter Register
ch23_ctrl: CH23_CTRL
0x4dc - Channel Descriptor Control Word Register
ch23_src: CH23_SRC
0x4e0 - Channel Descriptor Source Data Address Register
ch23_dst: CH23_DST
0x4e4 - Channel Descriptor Destination Data Address Register
ch23_link: CH23_LINK
0x4e8 - Channel Descriptor Link Structure Address Register