Enum efm32gg11b::eth::networkcfg::MDCCLKDIV_A [−][src]
#[repr(u8)] pub enum MDCCLKDIV_A { DIVBY8, DIVBY16, DIVBY32, DIVBY48, DIVBY64, DIVBY96, DIVBY128, DIVBY224, }
Expand description
MDC clock division
Value on reset: 2
Variants
0: divide HFBUSCLKETH by 8 (HFBUSCLKETH up to 20 MHz)
1: divide HFBUSCLKETH by 16 (HFBUSCLKETH up to 40 MHz)
2: divide HFBUSCLKETH by 32 (HFBUSCLKETH up to 80 MHz)
3: divide HFBUSCLKETH by 48 (HFBUSCLKETH up to 120 MHz)
4: divide HFBUSCLKETH by 64 (HFBUSCLKETH up to 160 MHz)
5: divide HFBUSCLKETH by 96 (HFBUSCLKETH up to 240 MHz)
6: divide HFBUSCLKETH by 128 (HFBUSCLKETH up to 320 MHz)
7: divide HFBUSCLKETH by 224 (HFBUSCLKETH up to 540 MHz)
Trait Implementations
Performs the conversion.