Struct efm32gg11b::can0::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {

    pub ctrl: CTRL,
    pub status: STATUS,
    pub errcnt: ERRCNT,
    pub bittiming: BITTIMING,
    pub intid: INTID,
    pub test: TEST,
    pub brpe: BRPE,
    pub transreq: TRANSREQ,
    pub messagedata: MESSAGEDATA,
    pub messagestate: MESSAGESTATE,
    pub config: CONFIG,
    pub if0if: IF0IF,
    pub if0ifs: IF0IFS,
    pub if0ifc: IF0IFC,
    pub if0ien: IF0IEN,
    pub if1if: IF1IF,
    pub if1ifs: IF1IFS,
    pub if1ifc: IF1IFC,
    pub if1ien: IF1IEN,
    pub route: ROUTE,
    pub mir0_cmdmask: MIR0_CMDMASK,
    pub mir0_mask: MIR0_MASK,
    pub mir0_arb: MIR0_ARB,
    pub mir0_ctrl: MIR0_CTRL,
    pub mir0_datal: MIR0_DATAL,
    pub mir0_datah: MIR0_DATAH,
    pub mir0_cmdreq: MIR0_CMDREQ,
    pub mir1_cmdmask: MIR1_CMDMASK,
    pub mir1_mask: MIR1_MASK,
    pub mir1_arb: MIR1_ARB,
    pub mir1_ctrl: MIR1_CTRL,
    pub mir1_datal: MIR1_DATAL,
    pub mir1_datah: MIR1_DATAH,
    pub mir1_cmdreq: MIR1_CMDREQ,
    // some fields omitted
}

Register block

Fields

ctrl: CTRL

0x00 - Control Register

status: STATUS

0x04 - Status Register

errcnt: ERRCNT

0x08 - Error Count Register

bittiming: BITTIMING

0x0c - Bit Timing Register

intid: INTID

0x10 - Interrupt Identification Register

test: TEST

0x14 - Test Register

brpe: BRPE

0x18 - BRP Extension Register

transreq: TRANSREQ

0x1c - Transmission Request Register

messagedata: MESSAGEDATA

0x20 - New Data Register

messagestate: MESSAGESTATE

0x28 - Message Valid Register

config: CONFIG

0x2c - Configuration Register

if0if: IF0IF

0x30 - Message Object Interrupt Flag Register

if0ifs: IF0IFS

0x34 - Message Object Interrupt Flag Set Register

if0ifc: IF0IFC

0x38 - Message Object Interrupt Flag Clear Register

if0ien: IF0IEN

0x3c - Message Object Interrupt Enable Register

if1if: IF1IF

0x40 - Status Interrupt Flag Register

if1ifs: IF1IFS

0x44 - Message Object Interrupt Flag Set Register

if1ifc: IF1IFC

0x48 - Message Object Interrupt Flag Clear Register

if1ien: IF1IEN

0x4c - Status Interrupt Enable Register

route: ROUTE

0x50 - I/O Routing Register

mir0_cmdmask: MIR0_CMDMASK

0x60 - Interface Command Mask Register

mir0_mask: MIR0_MASK

0x64 - Interface Mask Register

mir0_arb: MIR0_ARB

0x68 - Interface Arbitration Register

mir0_ctrl: MIR0_CTRL

0x6c - Interface Message Control Register

mir0_datal: MIR0_DATAL

0x70 - Interface Data a Register

mir0_datah: MIR0_DATAH

0x74 - Interface Data B Register

mir0_cmdreq: MIR0_CMDREQ

0x78 - Interface Command Request Register

mir1_cmdmask: MIR1_CMDMASK

0x80 - Interface Command Mask Register

mir1_mask: MIR1_MASK

0x84 - Interface Mask Register

mir1_arb: MIR1_ARB

0x88 - Interface Arbitration Register

mir1_ctrl: MIR1_CTRL

0x8c - Interface Message Control Register

mir1_datal: MIR1_DATAL

0x90 - Interface Data a Register

mir1_datah: MIR1_DATAH

0x94 - Interface Data B Register

mir1_cmdreq: MIR1_CMDREQ

0x98 - Interface Command Request Register