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extern crate embedded_hal as hal;
use super::super::{ Ds323x, SqWFreq, Register, BitFlags, Error };
use interface::{ ReadData, WriteData };
impl<DI, IC, E> Ds323x<DI, IC>
where
DI: ReadData<Error = E> + WriteData<Error = E>
{
pub fn enable(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control & !BitFlags::EOSC)
}
pub fn disable(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control | BitFlags::EOSC)
}
pub fn convert_temperature(&mut self) -> Result<(), Error<E>> {
let control = self.iface.read_register(Register::CONTROL)?;
if (control & BitFlags::TEMP_CONV) == 0 {
self.iface.write_register(Register::CONTROL, control | BitFlags::TEMP_CONV)?;
}
Ok(())
}
pub fn enable_32khz_output(&mut self) -> Result<(), Error<E>> {
let status = self.status | BitFlags::EN32KHZ;
self.write_status_without_clearing_alarm(status)
}
pub fn disable_32khz_output(&mut self) -> Result<(), Error<E>> {
let status = self.status & !BitFlags::EN32KHZ;
self.write_status_without_clearing_alarm(status)
}
pub fn set_aging_offset(&mut self, offset: i8) -> Result<(), Error<E>> {
self.iface.write_register(Register::AGING_OFFSET, offset as u8)
}
pub fn get_aging_offset(&mut self) -> Result<i8, Error<E>> {
let offset = self.iface.read_register(Register::AGING_OFFSET)?;
Ok(offset as i8)
}
pub fn use_int_sqw_output_as_interrupt(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control | BitFlags::INTCN)
}
pub fn use_int_sqw_output_as_square_wave(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control & !BitFlags::INTCN)
}
pub fn enable_square_wave(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control | BitFlags::BBSQW)
}
pub fn disable_square_wave(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control & !BitFlags::BBSQW)
}
pub fn set_square_wave_frequency(&mut self, freq: SqWFreq) -> Result<(), Error<E>> {
let new_control;
match freq {
SqWFreq::_1Hz => new_control = self.control & !BitFlags::RS2 & !BitFlags::RS1,
SqWFreq::_1_024Hz => new_control = self.control & !BitFlags::RS2 | BitFlags::RS1,
SqWFreq::_4_096Hz => new_control = self.control | BitFlags::RS2 & !BitFlags::RS1,
SqWFreq::_8_192Hz => new_control = self.control | BitFlags::RS2 | BitFlags::RS1,
}
self.write_control(new_control)
}
pub fn enable_alarm1_interrupts(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control | BitFlags::ALARM1_INT_EN)
}
pub fn disable_alarm1_interrupts(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control & !BitFlags::ALARM1_INT_EN)
}
pub fn enable_alarm2_interrupts(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control | BitFlags::ALARM2_INT_EN)
}
pub fn disable_alarm2_interrupts(&mut self) -> Result<(), Error<E>> {
let control = self.control;
self.write_control(control & !BitFlags::ALARM2_INT_EN)
}
fn write_control(&mut self, control: u8) -> Result<(), Error<E>> {
self.iface.write_register(Register::CONTROL, control)?;
self.control = control;
Ok(())
}
pub(crate) fn write_status_without_clearing_alarm(&mut self, status: u8) -> Result<(), Error<E>> {
let new_status = status | BitFlags::ALARM2F | BitFlags::ALARM1F;
self.iface.write_register(Register::STATUS, new_status)?;
self.status = status;
Ok(())
}
}