Struct cranelift::prelude::isa::x64::encoding::evex::EvexInstruction

pub struct EvexInstruction { /* private fields */ }

Constructs an EVEX-encoded instruction using a builder pattern. This approach makes it visually easier to transform something the manual’s syntax, EVEX.256.66.0F38.W1 1F /r to code: EvexInstruction::new().length(...).prefix(...).map(...).w(true).opcode(0x1F).reg(...).rm(...).

Implementations

impl EvexInstruction

pub fn new() -> EvexInstruction

Construct a default EVEX instruction.

pub fn length(self, length: EvexVectorLength) -> EvexInstruction

Set the length of the instruction . Note that there are sets of instructions (i.e. rounding, memory broadcast) that modify the same underlying bits–at some point (TODO) we can add a way to set those context bits and verify that both are not used (e.g. rounding AND length). For now, this method is very convenient.

pub fn prefix(self, prefix: LegacyPrefixes) -> EvexInstruction

Set the legacy prefix byte of the instruction: None | 66 | F0 | F2 | F3. EVEX instructions pack these into the prefix, not as separate bytes.

pub fn map(self, map: OpcodeMap) -> EvexInstruction

Set the opcode map byte of the instruction: None | 0F | 0F38 | 0F3A. EVEX instructions pack these into the prefix, not as separate bytes.

pub fn w(self, w: bool) -> EvexInstruction

Set the W bit, typically used to indicate an instruction using 64 bits of an operand (e.g. 64 bit lanes). EVEX packs this bit in the EVEX prefix; previous encodings used the REX prefix.

pub fn opcode(self, opcode: u8) -> EvexInstruction

Set the instruction opcode byte.

pub fn reg(self, reg: impl Into<Register>) -> EvexInstruction

Set the register to use for the reg bits; many instructions use this as the write operand. Setting this affects both the ModRM byte (reg section) and the EVEX prefix (the extension bits for register encodings > 8).

pub fn mask(self, mask: EvexMasking) -> EvexInstruction

Set the mask to use. See section 2.6 in the Intel Software Developer’s Manual, volume 2A for more details.

pub fn vvvvv(self, reg: impl Into<Register>) -> EvexInstruction

Set the vvvvv register; some instructions allow using this as a second, non-destructive source register in 3-operand instructions (e.g. 2 read, 1 write).

pub fn rm(self, reg: impl Into<Register>) -> EvexInstruction

Set the register to use for the rm bits; many instructions use this as the “read from register/memory” operand. Currently this does not support memory addressing (TODO).Setting this affects both the ModRM byte (rm section) and the EVEX prefix (the extension bits for register encodings > 8).

pub fn encode<CS>(&self, sink: &mut CS) where
    CS: ByteSink + ?Sized, 

Emit the EVEX-encoded instruction to the code sink:

• first, the 4-byte EVEX prefix;
• then, the opcode byte;
• finally, the ModR/M byte.

Eventually this method should support encodings of more than just the reg-reg addressing mode (TODO).

Trait Implementations

impl Default for EvexInstruction

Because some of the bit flags in the EVEX prefix are reversed and users of EvexInstruction may choose to skip setting fields, here we set some sane defaults. Note that:

• the first byte is always 0x62 but you will notice it at the end of the default bits value implemented–remember the little-endian order
• some bits are always set to certain values: bits 10-11 to 0, bit 18 to 1
• the other bits set correspond to reversed bits: R, X, B, R’ (byte 1), vvvv (byte 2), V’ (byte 3).

See the default_emission test for what these defaults are equivalent to (e.g. using RAX, unsetting the W bit, etc.)

fn default() -> EvexInstruction

Returns the “default value” for a type.