Crate cortex_m_asm[−][src]
Functions
Read the APSR register.
Write the BASEPRI_MAX register.
Read the BASEPRI register.
Write the BASEPRI register.
Puts the processor in Debug state. Debuggers can pick this up as a “breakpoint”.
Set CONTROL.SPSEL to 0, write msp to MSP, branch to rv.
Branch and Exchange Non-secure
Reads the CONTROL register.
Writes the CONTROL register.
Disables all interrupts.
Enables all interrupts.
Blocks the program for at least cycles CPU cycles.
Data Memory Barrier
Data Synchronization Barrier
Enable DCACHE.
Enable ICACHE.
Read the FAULTMASK register.
Instruction Synchronization Barrier
Read the LR register.
Write to the LR register.
Reads the Non-Secure MSP register from the Secure state.
Writes to the Non-Secure MSP register from the Secure state.
Read the MSP register.
Write the MSP register.
Reads the MSPLIM register.
Writes to the MSPLIM register.
A no-operation. Useful to prevent delay loops from being optimized away.
Read the PC register.
Write to the PC register.
Read the PRIMASK register.
Read the PSP register.
Write the PSP register.
Reads the PSPLIM register.
Writes to the PSPLIM register.
Send Event.
Semihosting syscall.
Test Target
Test Target Alternate Domain
Test Target Alternate Domain Unprivileged
Test Target Unprivileged
Generate an Undefined Instruction exception.
Wait For Event.
Wait For Interrupt.