Module cortex_a::registers::SCTLR_EL2

Modules

Alignment check enable. This is the enable bit for Alignment fault checking at EL2 and, when EL2 is enabled in the current Security state and HCR_EL2.{E2H, TGE} == {1, 1}, EL0.

C

Cacheability control, for data accesses.

EE

Exception endianness. The possible values are:

EIS

When FEAT_ExS is implemented control if taking an exception to EL2 is a context synchonizing event

I

Instruction Cache Control, two possible values:

IESB

When FEAT_IESB is implemented control if an implict ESB is added at each exception and before each ERET to/from EL2

M

MMU enable for EL2 or EL2&0 stage 1 address translation. Possible values of this bit are:

SA

SP Alignment check enable.

WXN

Force treatment of all memory regions with write permissions as XN. The possible values are:

Structs

Register

Constants