Modules
Selects whether TTBR0_EL1 or TTBR1_EL1 defines the ASID. The encoding of this bit is:
ASID Size. Defined values are:
Translation table walk disable for translations using TTBR0_EL1. This bit controls
whether a translation table walk is performed on a TLB miss, for an address that is
translated using TTBR0_EL1. The encoding of this bit is:
Translation table walk disable for translations using TTBR1_EL1. This bit controls
whether a translation table walk is performed on a TLB miss, for an address that is
translated using TTBR1_EL1. The encoding of this bit is:
When FEAT_HAFDBS is implemented hardware can update the access flags in the stage1
descriptors
When FEAT_HAFDBS is implemented hardware can update the dirty flags in the stage1
descriptors
Intermediate Physical Address Size.
Inner cacheability attribute for memory associated with translation table walks using
TTBR0_EL1.
Inner cacheability attribute for memory associated with translation
table walks using TTBR1_EL1.
Outer cacheability attribute for memory associated with translation table walks using
TTBR0_EL1.
Outer cacheability attribute for memory associated with translation table walks using
TTBR1_EL1.
Shareability attribute for memory associated with translation table walks using
TTBR0_EL1.
Shareability attribute for memory associated with translation table walks using
TTBR1_EL1.
The size offset of the memory region addressed by TTBR0_EL1. The region size is
2^(64-T0SZ) bytes.
The size offset of the memory region addressed by TTBR1_EL1. The region size is
2^(64-T1SZ) bytes.
Top Byte ignored - indicates whether the top byte of an address is used for address
match for the TTBR0_EL1 region, or ignored and used for tagged addresses. Defined values
are:
Top Byte ignored - indicates whether the top byte of an address is used for address
match for the TTBR1_EL1 region, or ignored and used for tagged addresses. Defined values
are:
When ARMv8.3-PAuth is implemented:
Controls the use of the top byte of instruction addresses for address matching.
0 TCR_EL1.TBI0 applies to Instruction and Data accesses.
1 TCR_EL1.TBI0 applies to Data accesses only.
This affects addresses where the address would be translated by tables pointed
to by TTBR0_EL1. This field resets to an architecturally UNKNOWN value.
Otherwise:
Reserved, RES0.
When ARMv8.3-PAuth is implemented:
Controls the use of the top byte of instruction addresses for address matching.
0 TCR_EL1.TBI1 applies to Instruction and Data accesses.
1 TCR_EL1.TBI1 applies to Data accesses only.
This affects addresses where the address would be translated by tables pointed
to by TTBR1_EL1. This field resets to an architecturally UNKNOWN value.
Otherwise:
Reserved, RES0.
Granule size for the TTBR0_EL1.
Granule size for the TTBR1_EL1.