Module cortex_a::registers::TCR_EL2

source · [−]

Modules

HA

When FEAT_HAFDBS is implemented hardware can update the access flags in the stage1 descriptors

HD

When FEAT_HAFDBS is implemented hardware can update the dirty flags in the stage1 descriptors

IRGN0

Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2.

ORGN0

Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2.

PS

Physical Address Size.

SH0

Shareability attribute for memory associated with translation table walks using TTBR0_EL2.

T0SZ

The size offset of the memory region addressed by TTBR0_EL2. The region size is 2^(64-T0SZ) bytes.

TBI

Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR0_EL2 region, or ignored and used for tagged addresses. Defined values are:

TG0

Granule size for the TTBR0_EL2.

Structs

Register

Constants