Expand description
Endianness of data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime.
0 Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are little-endian. 1 Explicit data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime are big-endian.
If an implementation does not provide Big-endian support at Exception Levels higher than EL0, this bit is RES 0.
If an implementation does not provide Little-endian support at Exception Levels higher than EL0, this bit is RES 1.
The EE bit is permitted to be cached in a TLB.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on the PE.
Enums
Endianness of data accesses at EL1, and stage 1 translation table walks in the EL1&0 translation regime.