Enum cortex_a::registers::HCR_EL2::VM::Value

#[repr(u64)]
pub enum Value {
    Disable,
    Enable,
}

Virtualization enable. Enables stage 2 address translation for the EL1&0 translation regime, when EL2 is enabled in the current Security state. The possible values are:

0 EL1&0 stage 2 address translation disabled. 1 EL1&0 stage 2 address translation enabled.

When the value of this bit is 1, data cache invalidate instructions executed at EL1 perform a data cache clean and invalidate. For the invalidate by set/way instruction this behavior applies regardless of the value of the HCR_EL2.SWIO bit.

This bit is permitted to be cached in a TLB.

When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this field behaves as 0 for all purposes other than a direct read of the value of this field.

Variants

Disable

Enable

Trait Implementations

impl TryFromValue<u64> for Value

type EnumType = Value

fn try_from(v: u64) -> Option<Self::EnumType>