Expand description
User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} masks to EL1, from AArch64 state only.
0 Any attempt at EL0 using AArch64 to execute an MRS , MSR(register) , or MSR(immediate)
instruction that accesses the DAIF is trapped to EL1.
1 This control does not cause any instructions to be trapped.
When ARMv8.1-VHE is implemented, and the value of HCR_EL2.{E2H, TGE} is {1, 1}, this bit has no effect on execution at EL0.
Enums
User Mask Access. Traps EL0 execution of MSR and MRS instructions that access the PSTATE.{D, A, I, F} masks to EL1, from AArch64 state only.