Module cortex_a::registers::TCR_EL2 [−][src]
Modules
Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL2.
Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL2.
Physical Address Size.
Shareability attribute for memory associated with translation table walks using TTBR0_EL2.
The size offset of the memory region addressed by TTBR0_EL2. The region size is 2^(64-T0SZ) bytes.
Top Byte ignored - indicates whether the top byte of an address is used for address match for the TTBR0_EL2 region, or ignored and used for tagged addresses. Defined values are:
Granule size for the TTBR0_EL2.