Enum cortex_a::registers::SCTLR_EL1::M::Value[][src]

#[repr(u64)]
pub enum Value {
    Disable,
    Enable,
}
Expand description

MMU enable for EL1 and EL0 stage 1 address translation. Possible values of this bit are:

0 EL1 and EL0 stage 1 address translation disabled.

  • See the SCTLR_EL1.I field for the behavior of instruction accesses to Normal memory.

1 EL1 and EL0 stage 1 address translation enabled.

Variants

Disable
Enable

Trait Implementations

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