Module cec1712_pac::led0
source · [−]Expand description
The LED is implemented using a PWM that can be driven either by the 48 MHz clock or by a 32.768 KHz clock input.
Modules
LED Configuration
LED Delay
LED Update Interval
LED Limits This register may be written at any time. Values written into the register are held in an holding register, which is transferred into the actual register at the end of a PWM period. The two byte fields may be written independently. Reads of this register return the current contents and not the value of the holding register.
LED Output Delay
This register has eight segment fields which provide the amount the current duty cycle is adjusted at the end of every PWM period. Segment field selection is decoded based on the segment index. The segment index equation utilized depends on the SYMMETRY bit in the LED Configuration Register Register) . In Symmetric Mode the Segment_Index[2:0] = Duty Cycle Bits[7:5] . In Asymmetric Mode the Segment_Index[2:0] is the bit concatenation of following: Segment_Index[2] = (FALLING RAMP TIME in Figure 30-3, Clipping Example) and Segment_Index[1:0] = Duty Cycle Bits[7:6].
Structs
Register block
Type Definitions
CFG (rw) register accessor: an alias for Reg<CFG_SPEC>
DLY (rw) register accessor: an alias for Reg<DLY_SPEC>
INTRVL (rw) register accessor: an alias for Reg<INTRVL_SPEC>
LIMIT (rw) register accessor: an alias for Reg<LIMIT_SPEC>
OUTDLY (rw) register accessor: an alias for Reg<OUTDLY_SPEC>
STEP (rw) register accessor: an alias for Reg<STEP_SPEC>