Module cec1712_pac::pwm0
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The PWM block generates an arbitrary duty cycle output at frequencies from less than 0.1 Hz to 24 MHz
Modules
PWMx CONFIGURATION REGISTER
This field determine both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the Off time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero, the PWM_OUTPUT is held high (Full On).
This field determines both the frequency and duty cycle of the PWM signal. Setting this field to a value of n will cause the On time of the PWM to be n+1 cycles of the PWM Clock Source. When this field is set to zero and the PWMX_COUNTER_OFF_TIME is not set to zero, the PWM_OUTPUT is held low (Full Off).
Structs
Register block