Module cec1712_pac::ec_reg_bank

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Expand description

This block is designed to be accessed internally by the EC via the register interface.

Modules

aesh_bswap_ctrl

AES HASH Byte Swap Control Register.

ahb_err_addr

AHB Error Address [0:0] AHB_ERR_ADDR, In priority order:

ahb_err_ctrl

AHB Error Control [0:0] AHB_ERROR_DISABLE, 0: EC memory exceptions are enabled. 1: EC memory exceptions are disabled.

brom_sts

This register contains the VTR Reset Status for BOOT ROM.

crypto_srst

System Shutdown Reset

debug_ctrl

Debug Enable Register

etm_ctrl

ETM TRACE Enable [0:0] TRACE_EN (TRACE_EN) This bit enables the ARM TRACE debug port (ETM/ITM). The Trace Debug Interface pins are forced to the TRACE functions. 0 = ARM TRACE port disabled, 1= ARM TRACE port enabled

fw_scr0

BOOT ROM Scratch 0 Register

fw_scr1

BOOT ROM Scratch 1 Register

fw_scr2

BOOT ROM Scratch 2 Register

fw_scr3

BOOT ROM Scratch 3 Register

gpio_bank_pwr

GPIO Bank Power Register

intr_ctrl

Interrupt Control [0:0] NVIC_EN (NVIC_EN) This bit enables Alternate NVIC IRQ’s Vectors. The Alternate NVIC Vectors provides each interrupt event with a dedicated (direct) NVIC vector. 0 = Alternate NVIC vectors disabled, 1= Alternate NVIC vectors enabled

jtag_mcfg

JTAG Master Configuration Register

jtag_mcmd

JTAG Master Command Register

jtag_msts

JTAG Master Status Register

jtag_mtdi

JTAG Master TDI Register

jtag_mtdo

JTAG Master TDO Register

jtag_mtms

JTAG Master TMS Register

otp_lock

Lock Register

peci_dis

PECI Disable

stap_tmir

This register is a mirror of the Boot Control Register.

wdt_cnt

WDT Event Count [3:0] WDT_COUNT (WDT_COUNT) These EC R/W bits are cleared to 0 on VCC1 POR, but not on a WDT. Note: This field is written by Boot ROM firmware to indicate the number of times a WDT fired before loading a good EC code image.