Module cec1712_pac::adc

Expand description

This block is designed to convert external analog voltage readings into digital values.

Modules

The ADC Configuration Register is used to configure the ADC clock timing.

All 16 ADC channels return their results into a 32-bit reading register. In each case the low 10 bits of the reading register return the result of the Analog to Digital conversion and the upper 22 bits return 0.

chan_sts

The ADC Status Register indicates whether the ADC has completed a conversion cycle. All bits are cleared by being written with a 1. 0: conversion of the corresponding ADC channel is not complete 1: conversion of the corresponding ADC channel is complete

ctrl

The ADC Control Register is used to control the behavior of the Analog to Digital Converter.

delay

The ADC Delay register determines the delay from setting Start_Repeat in the ADC Control Register and the start of a conversion cycle. This register also controls the interval between conversion cycles in repeat mode.

rept_en

The ADC Repeat Register is used to control which ADC channels are captured during a repeat conversion cycle initiated by the Start_Repeat bit in the ADC Control Register.

sar_cfg

This is the SAR ADC Configuration Register.

sar_ctrl

This is the SAR ADC Control Register.

sng_en

The ADC Single Register is used to control which ADC channel is captured during a Single-Sample conversion cycle initiated by the Start_Single bit in the ADC Control Register. APPLICATION NOTE: Do not change the bits in this register in the middle of a conversion cycle to insure proper operation. 0: single cycle conversions for this channel are disabled 1: single cycle conversions for this channel are enabled

vref_chan

The ADC Channel Register is used to configure the reference voltage to the clock timing.

vref_ctrl

This is the VREF Control Register