Module cc3220sf::i2s

I2S

Modules

aclkrctl	ACLKRCTL
aclkxctl	ACLKXCTL
ahclkrctl	AHCLKRCTL
ahclkxctl	AHCLKXCTL
amute	AMUTE
clkadjen	CLKADJEN
ditcsra0	DITCSRA0
ditcsra1	DITCSRA1
ditcsra2	DITCSRA2
ditcsra3	DITCSRA3
ditcsra4	DITCSRA4
ditcsra5	DITCSRA5
ditcsrb0	DITCSRB0
ditcsrb1	DITCSRB1
ditcsrb2	DITCSRB2
ditcsrb3	DITCSRB3
ditcsrb4	DITCSRB4
ditcsrb5	DITCSRB5
ditudra0	DITUDRA0
ditudra1	DITUDRA1
ditudra2	DITUDRA2
ditudra3	DITUDRA3
ditudra4	DITUDRA4
ditudra5	DITUDRA5
ditudrb0	DITUDRB0
ditudrb1	DITUDRB1
ditudrb2	DITUDRB2
ditudrb3	DITUDRB3
ditudrb4	DITUDRB4
ditudrb5	DITUDRB5
esysconfig	Power Idle SYSCONFIG register.
evtctlr	EVTCTLR
evtctlx	EVTCTLX
gblctl	GBLCTL
gblctlr	GBLCTLR
gblctlx	GBLCTLX
lbctl	LBCTL
pdclr	The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and if PFUNC = 1 (GPIO function) and PDIR = 1 (output) drives a logic low on the pin.
pdin_pdset	The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read regardless of the state of PFUNC and PDIR. The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDSET bit sets the corresponding bit in PDOUT and if PFUNC = 1 (GPIO function) and PDIR = 1 (output) drives a logic high on the pin.
pdir	PDIR
pdout	PDOUT
pfunc	PFUNC
pid	PID
revtctl	REVTCTL
rxbuf0	RXBUF0
rxbuf1	RXBUF1
rxbuf2	RXBUF2
rxbuf3	RXBUF3
rxbuf4	RXBUF4
rxbuf5	RXBUF5
rxbuf6	RXBUF6
rxbuf7	RXBUF7
rxbuf8	RXBUF8
rxbuf9	RXBUF9
rxbuf10	RXBUF10
rxbuf11	RXBUF11
rxbuf12	RXBUF12
rxbuf13	RXBUF13
rxbuf14	RXBUF14
rxbuf15	RXBUF15
rxclkchk	RXCLKCHK
rxfmctl	RXFMCTL
rxfmt	RXFMT
rxmask	RXMASK
rxstat	RXSTAT
rxtdm	RXTDM
rxtdmslot	RXTDMSLOT
tlec	for IODFT
tlgc	for IODFT
tlmr	for IODFT
txbuf0	TXBUF0
txbuf1	TXBUF1
txbuf2	TXBUF2
txbuf3	TXBUF3
txbuf4	TXBUF4
txbuf5	TXBUF5
txbuf6	TXBUF6
txbuf7	TXBUF7
txbuf8	TXBUF8
txbuf9	TXBUF9
txbuf10	TXBUF10
txbuf11	TXBUF11
txbuf12	TXBUF12
txbuf13	TXBUF13
txbuf14	TXBUF14
txbuf15	TXBUF15
txclkchk	TXCLKCHK
txditctl	TXDITCTL
txfmctl	TXFMCTL
txfmt	TXFMT
txmask	TXMASK
txstat	TXSTAT
txtdm	TXTDM
txtdmslot	TXTDMSLOT
xevtctl	XEVTCTL
xrsrctl0	XRSRCTL0
xrsrctl1	XRSRCTL1
xrsrctl2	XRSRCTL2
xrsrctl3	XRSRCTL3
xrsrctl4	XRSRCTL4
xrsrctl5	XRSRCTL5
xrsrctl6	XRSRCTL6
xrsrctl7	XRSRCTL7
xrsrctl8	XRSRCTL8
xrsrctl9	XRSRCTL9
xrsrctl10	XRSRCTL10
xrsrctl11	XRSRCTL11
xrsrctl12	XRSRCTL12
xrsrctl13	XRSRCTL13
xrsrctl14	XRSRCTL14
xrsrctl15	XRSRCTL15

Structs

RegisterBlock

Register block

Type Definitions

ACLKRCTL	ACLKRCTL
ACLKXCTL	ACLKXCTL
AHCLKRCTL	AHCLKRCTL
AHCLKXCTL	AHCLKXCTL
AMUTE	AMUTE
CLKADJEN	CLKADJEN
DITCSRA0	DITCSRA0
DITCSRA1	DITCSRA1
DITCSRA2	DITCSRA2
DITCSRA3	DITCSRA3
DITCSRA4	DITCSRA4
DITCSRA5	DITCSRA5
DITCSRB0	DITCSRB0
DITCSRB1	DITCSRB1
DITCSRB2	DITCSRB2
DITCSRB3	DITCSRB3
DITCSRB4	DITCSRB4
DITCSRB5	DITCSRB5
DITUDRA0	DITUDRA0
DITUDRA1	DITUDRA1
DITUDRA2	DITUDRA2
DITUDRA3	DITUDRA3
DITUDRA4	DITUDRA4
DITUDRA5	DITUDRA5
DITUDRB0	DITUDRB0
DITUDRB1	DITUDRB1
DITUDRB2	DITUDRB2
DITUDRB3	DITUDRB3
DITUDRB4	DITUDRB4
DITUDRB5	DITUDRB5
ESYSCONFIG	Power Idle SYSCONFIG register.
EVTCTLR	EVTCTLR
EVTCTLX	EVTCTLX
GBLCTL	GBLCTL
GBLCTLR	GBLCTLR
GBLCTLX	GBLCTLX
LBCTL	LBCTL
PDCLR	The pin data clear register (PDCLR) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDCLR bit clears the corresponding bit in PDOUT and if PFUNC = 1 (GPIO function) and PDIR = 1 (output) drives a logic low on the pin.
PDIN_PDSET	The pin data input register (PDIN) holds the I/O pin state of each of the McASP pins. PDIN allows the actual value of the pin to be read regardless of the state of PFUNC and PDIR. The pin data set register (PDSET) is an alias of the pin data output register (PDOUT) for writes only. Writing a 1 to the PDSET bit sets the corresponding bit in PDOUT and if PFUNC = 1 (GPIO function) and PDIR = 1 (output) drives a logic high on the pin.
PDIR	PDIR
PDOUT	PDOUT
PFUNC	PFUNC
PID	PID
REVTCTL	REVTCTL
RXBUF0	RXBUF0
RXBUF1	RXBUF1
RXBUF2	RXBUF2
RXBUF3	RXBUF3
RXBUF4	RXBUF4
RXBUF5	RXBUF5
RXBUF6	RXBUF6
RXBUF7	RXBUF7
RXBUF8	RXBUF8
RXBUF9	RXBUF9
RXBUF10	RXBUF10
RXBUF11	RXBUF11
RXBUF12	RXBUF12
RXBUF13	RXBUF13
RXBUF14	RXBUF14
RXBUF15	RXBUF15
RXCLKCHK	RXCLKCHK
RXFMCTL	RXFMCTL
RXFMT	RXFMT
RXMASK	RXMASK
RXSTAT	RXSTAT
RXTDM	RXTDM
RXTDMSLOT	RXTDMSLOT
TLEC	for IODFT
TLGC	for IODFT
TLMR	for IODFT
TXBUF0	TXBUF0
TXBUF1	TXBUF1
TXBUF2	TXBUF2
TXBUF3	TXBUF3
TXBUF4	TXBUF4
TXBUF5	TXBUF5
TXBUF6	TXBUF6
TXBUF7	TXBUF7
TXBUF8	TXBUF8
TXBUF9	TXBUF9
TXBUF10	TXBUF10
TXBUF11	TXBUF11
TXBUF12	TXBUF12
TXBUF13	TXBUF13
TXBUF14	TXBUF14
TXBUF15	TXBUF15
TXCLKCHK	TXCLKCHK
TXDITCTL	TXDITCTL
TXFMCTL	TXFMCTL
TXFMT	TXFMT
TXMASK	TXMASK
TXSTAT	TXSTAT
TXTDM	TXTDM
TXTDMSLOT	TXTDMSLOT
XEVTCTL	XEVTCTL
XRSRCTL0	XRSRCTL0
XRSRCTL1	XRSRCTL1
XRSRCTL2	XRSRCTL2
XRSRCTL3	XRSRCTL3
XRSRCTL4	XRSRCTL4
XRSRCTL5	XRSRCTL5
XRSRCTL6	XRSRCTL6
XRSRCTL7	XRSRCTL7
XRSRCTL8	XRSRCTL8
XRSRCTL9	XRSRCTL9
XRSRCTL10	XRSRCTL10
XRSRCTL11	XRSRCTL11
XRSRCTL12	XRSRCTL12
XRSRCTL13	XRSRCTL13
XRSRCTL14	XRSRCTL14
XRSRCTL15	XRSRCTL15