Module cc3220sf::stackdie_ctrl::stk_sr_acc_ctl_bk2

In Spinlock mode this Register defines who among base processor and stack processor have access to Sram Bank2 right now. In Handshake mode this Register defines who among base processor and stack processor have access to Sram Bank2 and Bank3 right now. Its Clear only register and is set by hardware. Lower bit can be cleared only by Base Processor and Upper bit Cleared only by the Stack processor.

Type Definitions

R	Reader of register STK_SR_ACC_CTL_BK2
W	Writer for register STK_SR_ACC_CTL_BK2