[−][src]Type Definition cc3220sf::gprcm::mem_hclk_div_cfg::R
type R = R<u32, MEM_HCLK_DIV_CFG>;
Reader of register MEM_HCLK_DIV_CFG
Implementations
impl R
[src]
pub fn mem_hclk_div_cfg(&self) -> MEM_HCLK_DIV_CFG_R
[src]
Bits 0:2 - Division configuration for HCLKDIVOUT : "000" - Divide by 1 ; "001" - Divide by 2 ; "010" - Divide by 3 ; "011" - Divide by 4 ; "100" - Divide by 5 ; "101" - Divide by 6 ; "110" - Divide by 7 ; "111" - Divide by 8