Struct cc2650::cpu_itm::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub stim0: STIM0,
    pub stim1: STIM1,
    pub stim2: STIM2,
    pub stim3: STIM3,
    pub stim4: STIM4,
    pub stim5: STIM5,
    pub stim6: STIM6,
    pub stim7: STIM7,
    pub stim8: STIM8,
    pub stim9: STIM9,
    pub stim10: STIM10,
    pub stim11: STIM11,
    pub stim12: STIM12,
    pub stim13: STIM13,
    pub stim14: STIM14,
    pub stim15: STIM15,
    pub stim16: STIM16,
    pub stim17: STIM17,
    pub stim18: STIM18,
    pub stim19: STIM19,
    pub stim20: STIM20,
    pub stim21: STIM21,
    pub stim22: STIM22,
    pub stim23: STIM23,
    pub stim24: STIM24,
    pub stim25: STIM25,
    pub stim26: STIM26,
    pub stim27: STIM27,
    pub stim28: STIM28,
    pub stim29: STIM29,
    pub stim30: STIM30,
    pub stim31: STIM31,
    pub ter: TER,
    pub tpr: TPR,
    pub tcr: TCR,
    pub lar: LAR,
    pub lsr: LSR,
    // some fields omitted
}

Register block

Fields

stim0: STIM0

0x00 - Stimulus Port 0

stim1: STIM1

0x04 - Stimulus Port 1

stim2: STIM2

0x08 - Stimulus Port 2

stim3: STIM3

0x0c - Stimulus Port 3

stim4: STIM4

0x10 - Stimulus Port 4

stim5: STIM5

0x14 - Stimulus Port 5

stim6: STIM6

0x18 - Stimulus Port 6

stim7: STIM7

0x1c - Stimulus Port 7

stim8: STIM8

0x20 - Stimulus Port 8

stim9: STIM9

0x24 - Stimulus Port 9

stim10: STIM10

0x28 - Stimulus Port 10

stim11: STIM11

0x2c - Stimulus Port 11

stim12: STIM12

0x30 - Stimulus Port 12

stim13: STIM13

0x34 - Stimulus Port 13

stim14: STIM14

0x38 - Stimulus Port 14

stim15: STIM15

0x3c - Stimulus Port 15

stim16: STIM16

0x40 - Stimulus Port 16

stim17: STIM17

0x44 - Stimulus Port 17

stim18: STIM18

0x48 - Stimulus Port 18

stim19: STIM19

0x4c - Stimulus Port 19

stim20: STIM20

0x50 - Stimulus Port 20

stim21: STIM21

0x54 - Stimulus Port 21

stim22: STIM22

0x58 - Stimulus Port 22

stim23: STIM23

0x5c - Stimulus Port 23

stim24: STIM24

0x60 - Stimulus Port 24

stim25: STIM25

0x64 - Stimulus Port 25

stim26: STIM26

0x68 - Stimulus Port 26

stim27: STIM27

0x6c - Stimulus Port 27

stim28: STIM28

0x70 - Stimulus Port 28

stim29: STIM29

0x74 - Stimulus Port 29

stim30: STIM30

0x78 - Stimulus Port 30

stim31: STIM31

0x7c - Stimulus Port 31

ter: TER

0xe00 - Trace Enable Use the Trace Enable Register to generate trace data by writing to the corresponding stimulus port. Note: Privileged writes are accepted to this register if TCR.ITMENA is set. User writes are accepted to this register if TCR.ITMENA is set and the appropriate privilege mask is cleared. Privileged access to the stimulus ports enables an RTOS kernel to guarantee instrumentation slots or bandwidth as required.

tpr: TPR

0xe40 - Trace Privilege This register is used to enable an operating system to control which stimulus ports are accessible by user code. This register can only be used in privileged mode.

tcr: TCR

0xe80 - Trace Control Use this register to configure and control ITM transfers. This register can only be written in privilege mode. DWT is not enabled in the ITM block. However, DWT stimulus entry into the FIFO is controlled by DWTENA. If DWT requires timestamping, the TSENA bit must be set.

lar: LAR

0xfb0 - Lock Access This register is used to prevent write accesses to the Control Registers: TER, TPR and TCR.

lsr: LSR

0xfb4 - Lock Status Use this register to enable write accesses to the Control Register.