Struct cc2650::crypto::aesctl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn context_rdy(&self) -> CONTEXT_RDYR

Bit 31 - If 1, this status bit indicates that the context data registers can be overwritten and the Host is permitted to write the next context. Writing a context means writing either a mode, the crypto length or AESDATALEN1.LEN_MSW, AESDATALEN0.LEN_LSW length registers

pub fn saved_context_rdy(&self) -> SAVED_CONTEXT_RDYR

Bit 30 - If read as 1, this status bit indicates that an AES authentication TAG and/or IV block(s) is/are available for the Host to retrieve. This bit is only asserted if SAVE_CONTEXT is set to 1. The bit is mutually exclusive with CONTEXT_RDY. Writing 1 clears the bit to zero, indicating the Crypto peripheral can start its next operation. This bit is also cleared when the 4th word of the output TAG and/or IV is read. Note: All other mode bit writes will be ignored when this mode bit is written with 1. Note: This bit is controlled automatically by the Crypto peripheral for TAG read DMA operations. For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral.

pub fn save_context(&self) -> SAVE_CONTEXTR

Bit 29 - IV must be read before the AES engine can start a new operation.

pub fn reserved25(&self) -> RESERVED25R

Bits 25:28 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn ccm_m(&self) -> CCM_MR

Bits 22:24 - Defines M that indicates the length of the authentication field for CCM operations; the authentication field length equals two times the value of CCM_M plus one. Note: The Crypto peripheral always returns a 128-bit authentication field, of which the M least significant bytes are valid. All values are supported.

pub fn ccm_l(&self) -> CCM_LR

Bits 19:21 - Defines L that indicates the width of the length field for CCM operations; the length field in bytes equals the value of CMM_L plus one. All values are supported.

pub fn ccm(&self) -> CCMR

Bit 18 - AES-CCM mode enable. AES-CCM is a combined mode, using AES for both authentication and encryption. Note: Selecting AES-CCM mode requires writing of AESDATALEN1.LEN_MSW and AESDATALEN0.LEN_LSW after all other registers. Note: The CTR mode bit in this register must also be set to 1 to enable AES-CTR; selecting other AES modes than CTR mode is invalid.

pub fn cbc_mac(&self) -> CBC_MACR

Bit 15 - MAC mode enable. The DIR bit must be set to 1 for this mode. Selecting this mode requires writing the AESDATALEN1.LEN_MSW and AESDATALEN0.LEN_LSW registers after all other registers.

pub fn reserved9(&self) -> RESERVED9R

Bits 9:14 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn ctr_width(&self) -> CTR_WIDTHR

Bits 7:8 - Specifies the counter width for AES-CTR mode

pub fn ctr(&self) -> CTRR

Bit 6 - AES-CTR mode enable This bit must also be set for CCM, when encryption/decryption is required.

pub fn cbc(&self) -> CBCR

Bit 5 - CBC mode enable

pub fn key_size(&self) -> KEY_SIZER

Bits 3:4 - This field specifies the key size. The key size is automatically configured when a new key is loaded via the key store module. 00 = N/A - reserved 01 = 128 bits 10 = N/A - reserved 11 = N/A - reserved For the Crypto peripheral this field is fixed to 128 bits.

pub fn dir(&self) -> DIRR

Bit 2 - Direction. 0 : Decrypt operation is performed. 1 : Encrypt operation is performed. This bit must be written with a 1 when CBC-MAC is selected.

pub fn input_rdy(&self) -> INPUT_RDYR

Bit 1 - If read as 1, this status bit indicates that the 16-byte AES input buffer is empty. The Host is permitted to write the next block of data. Writing a 0 clears the bit to zero and indicates that the AES engine can use the provided input data block. Writing a 1 to this bit will be ignored. Note: For DMA operations, this bit is automatically controlled by the Crypto peripheral. After reset, this bit is 0. After writing a context (note 1), this bit will become 1. For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral.

pub fn output_rdy(&self) -> OUTPUT_RDYR

Bit 0 - If read as 1, this status bit indicates that an AES output block is available to be retrieved by the Host. Writing a 0 clears the bit to zero and indicates that output data is read by the Host. The AES engine can provide a next output data block. Writing a 1 to this bit will be ignored. Note: For DMA operations, this bit is automatically controlled by the Crypto peripheral. For typical use, this bit does NOT need to be written, but is used for status reading only. In this case, this status bit is automatically maintained by the Crypto peripheral.