Struct cc2650::cpu_scs::demcr::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved25(&self) -> RESERVED25R

Bits 25:31 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn trcena(&self) -> TRCENAR

Bit 24 - This bit must be set to 1 to enable use of the trace and debug blocks: DWT, ITM, ETM and TPIU. This enables control of power usage unless tracing is required. The application can enable this, for ITM use, or use by a debugger.

pub fn reserved20(&self) -> RESERVED20R

Bits 20:23 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn mon_req(&self) -> MON_REQR

Bit 19 - This enables the monitor to identify how it wakes up. This bit clears on a Core Reset. 0x0: Woken up by debug exception. 0x1: Woken up by MON_PEND

pub fn mon_step(&self) -> MON_STEPR

Bit 18 - When MON_EN = 1, this steps the core. When MON_EN = 0, this bit is ignored. This is the equivalent to DHCSR.C_STEP. Interrupts are only stepped according to the priority of the monitor and settings of PRIMASK, FAULTMASK, or BASEPRI.

pub fn mon_pend(&self) -> MON_PENDR

Bit 17 - Pend the monitor to activate when priority permits. This can wake up the monitor through the AHB-AP port. It is the equivalent to DHCSR.C_HALT for Monitor debug. This register does not reset on a system reset. It is only reset by a power-on reset. Software in the reset handler or later, or by the DAP must enable the debug monitor.

pub fn mon_en(&self) -> MON_ENR

Bit 16 - Enable the debug monitor. When enabled, the System handler priority register controls its priority level. If disabled, then all debug events go to Hard fault. DHCSR.C_DEBUGEN overrides this bit. Vector catching is semi-synchronous. When a matching event is seen, a Halt is requested. Because the processor can only halt on an instruction boundary, it must wait until the next instruction boundary. As a result, it stops on the first instruction of the exception handler. However, two special cases exist when a vector catch has triggered: 1. If a fault is taken during vectoring, vector read or stack push error, the halt occurs on the corresponding fault handler, for the vector error or stack push. 2. If a late arriving interrupt comes in during vectoring, it is not taken. That is, an implementation that supports the late arrival optimization must suppress it in this case.

pub fn reserved11(&self) -> RESERVED11R

Bits 11:15 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn vc_harderr(&self) -> VC_HARDERRR

Bit 10 - Debug trap on Hard Fault. Ignored when DHCSR.C_DEBUGEN is cleared.

pub fn vc_interr(&self) -> VC_INTERRR

Bit 9 - Debug trap on a fault occurring during an exception entry or return sequence. Ignored when DHCSR.C_DEBUGEN is cleared.

pub fn vc_buserr(&self) -> VC_BUSERRR

Bit 8 - Debug Trap on normal Bus error. Ignored when DHCSR.C_DEBUGEN is cleared.

pub fn vc_staterr(&self) -> VC_STATERRR

Bit 7 - Debug trap on Usage Fault state errors. Ignored when DHCSR.C_DEBUGEN is cleared.

pub fn vc_chkerr(&self) -> VC_CHKERRR

Bit 6 - Debug trap on Usage Fault enabled checking errors. Ignored when DHCSR.C_DEBUGEN is cleared.

pub fn vc_nocperr(&self) -> VC_NOCPERRR

Bit 5 - Debug trap on a UsageFault access to a Coprocessor. Ignored when DHCSR.C_DEBUGEN is cleared.

pub fn vc_mmerr(&self) -> VC_MMERRR

Bit 4 - Debug trap on Memory Management faults. Ignored when DHCSR.C_DEBUGEN is cleared.

pub fn reserved1(&self) -> RESERVED1R

Bits 1:3 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn vc_corereset(&self) -> VC_CORERESETR

Bit 0 - Reset Vector Catch. Halt running system if Core reset occurs. Ignored when DHCSR.C_DEBUGEN is cleared.