Struct cc2650::aon_sysctl::resetctl::R

pub struct R { /* fields omitted */ }

Value read from the register

Methods

impl R

pub fn bits(&self) -> u32

Value of the register as raw bits

pub fn reserved26(&self) -> RESERVED26R

Bits 26:30 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn boot_det_1_clr(&self) -> BOOT_DET_1_CLRR

Bit 25 - Internal. Only to be used through TI provided API.

pub fn boot_det_0_clr(&self) -> BOOT_DET_0_CLRR

Bit 24 - Internal. Only to be used through TI provided API.

pub fn reserved18(&self) -> RESERVED18R

Bits 18:23 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn boot_det_1_set(&self) -> BOOT_DET_1_SETR

Bit 17 - Internal. Only to be used through TI provided API.

pub fn boot_det_0_set(&self) -> BOOT_DET_0_SETR

Bit 16 - Internal. Only to be used through TI provided API.

pub fn wu_from_sd(&self) -> WU_FROM_SDR

Bit 15 - A Wakeup from SHUTDOWN on an IO event has occurred, or a wakeup from SHUTDOWN has occurred as a result of the debugger being attached.. (TCK pin being forced low) Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup sources. 0: Wakeup occurred from cold reset or brown out as seen in RESET_SRC 1: A wakeup has occurred from SHUTDOWN Note: This flag can not be cleared and will therefor remain valid untill poweroff/reset

pub fn gpio_wu_from_sd(&self) -> GPIO_WU_FROM_SDR

Bit 14 - A wakeup from SHUTDOWN on an IO event has occurred Please refer to [IOC:IOCFGn,.WU_CFG] for configuring the IO's as wakeup sources. 0: The wakeup did not occur from SHUTDOWN on an IO event 1: A wakeup from SHUTDOWN occurred from an IO event The case where WU_FROM_SD is asserted but this bitfield is not asserted will only occur in a debug session. The boot code will not proceed with wakeup from SHUTDOWN procedure until this bitfield is asserted as well. Note: This flag can not be cleared and will therefor remain valid untill poweroff/reset

pub fn boot_det_1(&self) -> BOOT_DET_1R

Bit 13 - Internal. Only to be used through TI provided API.

pub fn boot_det_0(&self) -> BOOT_DET_0R

Bit 12 - Internal. Only to be used through TI provided API.

pub fn vdds_loss_en_ovr(&self) -> VDDS_LOSS_EN_OVRR

Bit 11 - Override of VDDS_LOSS_EN 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN=1 1: Brown out detect of VDDS generates system reset (regardless of VDDS_LOSS_EN) This bit can be locked

pub fn vddr_loss_en_ovr(&self) -> VDDR_LOSS_EN_OVRR

Bit 10 - Override of VDDR_LOSS_EN 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN=1 1: Brown out detect of VDDR generates system reset (regardless of VDDR_LOSS_EN) This bit can be locked

pub fn vdd_loss_en_ovr(&self) -> VDD_LOSS_EN_OVRR

Bit 9 - Override of VDD_LOSS_EN 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN=1 1: Brown out detect of VDD generates system reset (regardless of VDD_LOSS_EN) This bit can be locked

pub fn reserved8(&self) -> RESERVED8R

Bit 8 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn vdds_loss_en(&self) -> VDDS_LOSS_ENR

Bit 7 - Controls reset generation in case VDDS is lost 0: Brown out detect of VDDS is ignored, unless VDDS_LOSS_EN_OVR=1 1: Brown out detect of VDDS generates system reset

pub fn vddr_loss_en(&self) -> VDDR_LOSS_ENR

Bit 6 - Controls reset generation in case VDDR is lost 0: Brown out detect of VDDR is ignored, unless VDDR_LOSS_EN_OVR=1 1: Brown out detect of VDDR generates system reset

pub fn vdd_loss_en(&self) -> VDD_LOSS_ENR

Bit 5 - Controls reset generation in case VDD is lost 0: Brown out detect of VDD is ignored, unless VDD_LOSS_EN_OVR=1 1: Brown out detect of VDD generates system reset

pub fn clk_loss_en(&self) -> CLK_LOSS_ENR

Bit 4 - Controls reset generation in case SCLK_LF is lost. (provided that clock loss detection is enabled by DDI_0_OSC:CTL0.CLK_LOSS_EN) Note: Clock loss reset generation must be disabled before SCLK_LF clock source is changed in DDI_0_OSC:CTL0.SCLK_LF_SRC_SEL and remain disabled untill the change is confirmed in DDI_0_OSC:STAT0.SCLK_LF_SRC. Failure to do so may result in a spurious system reset. Clock loss reset generation can be disabled through this bitfield or by clearing DDI_0_OSC:CTL0.CLK_LOSS_EN 0: Clock loss is ignored 1: Clock loss generates system reset

pub fn reset_src(&self) -> RESET_SRCR

Bits 1:3 - Shows the source of the last system reset: Occurrence of one of the reset sources may trigger several other reset sources as essential parts of the system are undergoing reset. This field will report the root cause of the reset (not the other resets that are consequence of the system reset). To support this feature the actual register is not captured before the reset source being released. If a new reset source is triggered, in a window of four 32 kHz periods after the previous has been released, this register may indicate Power on reset as source.

pub fn reserved0(&self) -> RESERVED0R

Bit 0 - Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.