Struct cc13x2_cc26x2_hal::crypto::irqstat::W

pub struct W { /* fields omitted */ }

Value to write to the register

Methods

impl W

pub fn reset_value() -> W

Reset value of the register

pub unsafe fn bits(&mut self, bits: u32) -> &mut Self

Writes raw bits to the register

pub fn dma_bus_err(&mut self) -> _DMA_BUS_ERRW

Bit 31 - 31:31] This bit is set when a DMA bus error is detected during a DMA operation. The value of this register is held until it is cleared through the IRQCLR.DMA_BUS_ERR Note: This error is asserted if an error is detected on the AHB master interface during a DMA operation.

pub fn key_st_wr_err(&mut self) -> _KEY_ST_WR_ERRW

Bit 30 - 30:30] This bit is set when a write error is detected during the DMA write operation to the key store memory. The value of this register is held until it is cleared through the IRQCLR.KEY_ST_WR_ERR register. Note: This error is asserted if a DMA operation does not cover a full key area or more areas are written than expected.

pub fn key_st_rd_err(&mut self) -> _KEY_ST_RD_ERRW

Bit 29 - 29:29] This bit is set when a read error is detected during the read of a key from the key store, while copying it to the AES core. The value of this register is held until it is cleared through the IRQCLR.KEY_ST_RD_ERR register. Note: This error is asserted if a key location is selected in the key store that is not available.

pub fn reserved2(&mut self) -> _RESERVED2W

Bits 2:28 - 28:2] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.

pub fn dma_in_done(&mut self) -> _DMA_IN_DONEW

Bit 1 - 1:1] This read only bit returns the actual DMA data in done (irq_data_in_done) interrupt status of the DMA data in done interrupt output pin (irq_data_in_done).

pub fn result_avail(&mut self) -> _RESULT_AVAILW

Bit 0 - 0:0] This read only bit returns the actual result available (irq_result_av) interrupt status of the result available interrupt output pin (irq_result_av).