[−][src]Struct cc13x2_cc26x2_hal::aux_ddi0_osc::ctl0::R
Value read from the register
Methods
impl R
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pub fn bits(&self) -> u32
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Value of the register as raw bits
pub fn xtal_is_24m(&self) -> XTAL_IS_24MR
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Bit 31 - 31:31] Set based on the accurate high frequency XTAL.
pub fn reserved30(&self) -> RESERVED30R
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Bit 30 - 30:30] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn bypass_xosc_lf_clk_qual(&self) -> BYPASS_XOSC_LF_CLK_QUALR
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Bit 29 - 29:29] Internal. Only to be used through TI provided API.
pub fn bypass_rcosc_lf_clk_qual(&self) -> BYPASS_RCOSC_LF_CLK_QUALR
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Bit 28 - 28:28] Internal. Only to be used through TI provided API.
pub fn doubler_start_duration(&self) -> DOUBLER_START_DURATIONR
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Bits 26:27 - 27:26] Internal. Only to be used through TI provided API.
pub fn doubler_reset_duration(&self) -> DOUBLER_RESET_DURATIONR
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Bit 25 - 25:25] Internal. Only to be used through TI provided API.
pub fn clk_dcdc_src_sel(&self) -> CLK_DCDC_SRC_SELR
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Bit 24 - 24:24] Select DCDC clock source. 0: CLK_DCDC is 48 MHz clock from RCOSC or XOSC / HPOSC 1: CLK_DCDC is always 48 MHz clock from RCOSC
pub fn reserved15(&self) -> RESERVED15R
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Bits 15:23 - 23:15] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn hposc_mode_en(&self) -> HPOSC_MODE_ENR
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Bit 14 - 14:14] Internal. Only to be used through TI provided API.
pub fn reserved13(&self) -> RESERVED13R
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Bit 13 - 13:13] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn rcosc_lf_trimmed(&self) -> RCOSC_LF_TRIMMEDR
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Bit 12 - 12:12] Internal. Only to be used through TI provided API.
pub fn xosc_hf_power_mode(&self) -> XOSC_HF_POWER_MODER
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Bit 11 - 11:11] Internal. Only to be used through TI provided API.
pub fn xosc_lf_dig_bypass(&self) -> XOSC_LF_DIG_BYPASSR
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Bit 10 - 10:10] Bypass XOSC_LF and use the digital input clock from AON for the xosc_lf clock. 0: Use 32kHz XOSC as xosc_lf clock source 1: Use digital input (from AON) as xosc_lf clock source. This bit will only have effect when SCLK_LF_SRC_SEL is selecting the xosc_lf as the sclk_lf source. The muxing performed by this bit is not glitch free. The following procedure must be followed when changing this field to avoid glitches on sclk_lf. 1) Set SCLK_LF_SRC_SEL to select any source other than the xosc_lf clock source. 2) Set or clear this bit to bypass or not bypass the xosc_lf. 3) Set SCLK_LF_SRC_SEL to use xosc_lf. It is recommended that either the rcosc_hf or xosc_hf (whichever is currently active) be selected as the source in step 1 above. This provides a faster clock change.
pub fn clk_loss_en(&self) -> CLK_LOSS_ENR
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Bit 9 - 9:9] Enable clock loss detection and hence the indicators to the system controller. Checks both SCLK_HF, SCLK_MF and SCLK_LF clock loss indicators. 0: Disable 1: Enable Clock loss detection must be disabled when changing the sclk_lf source. STAT0.SCLK_LF_SRC can be polled to determine when a change to a new sclk_lf source has completed.
pub fn aclk_tdc_src_sel(&self) -> ACLK_TDC_SRC_SELR
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Bits 7:8 - 8:7] Source select for aclk_tdc. 00: RCOSC_HF (48MHz) 01: RCOSC_HF (24MHz) 10: XOSC_HF (24MHz) 11: Not used
pub fn aclk_ref_src_sel(&self) -> ACLK_REF_SRC_SELR
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Bits 4:6 - 6:4] Source select for aclk_ref 000: RCOSC_HF derived (31.25kHz) 001: XOSC_HF derived (31.25kHz) 010: RCOSC_LF (32kHz) 011: XOSC_LF (32.768kHz) 100: RCOSC_MF (2MHz) 101-111: Not used
pub fn sclk_lf_src_sel(&self) -> SCLK_LF_SRC_SELR
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Bits 2:3 - 3:2] Source select for sclk_lf
pub fn reserved1(&self) -> RESERVED1R
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Bit 1 - 1:1] Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior.
pub fn sclk_hf_src_sel(&self) -> SCLK_HF_SRC_SELR
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Bit 0 - 0:0] Source select for sclk_hf.
Auto Trait Implementations
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U: From<T>,
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U: From<T>,
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T: ?Sized,
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T: 'static + ?Sized,
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