Struct cc13x2_cc26x2_hal::aux_anaif::RegisterBlock

#[repr(C)]
pub struct RegisterBlock {
    pub adcctl: ADCCTL,
    pub adcfifostat: ADCFIFOSTAT,
    pub adcfifo: ADCFIFO,
    pub adctrig: ADCTRIG,
    pub isrcctl: ISRCCTL,
    pub dacctl: DACCTL,
    pub lpmbiasctl: LPMBIASCTL,
    pub dacsmplctl: DACSMPLCTL,
    pub dacsmplcfg0: DACSMPLCFG0,
    pub dacsmplcfg1: DACSMPLCFG1,
    pub dacvalue: DACVALUE,
    pub dacstat: DACSTAT,
    // some fields omitted
}

Register block

Fields

adcctl: ADCCTL

0x10 - ADC Control Configuration of ADI_4_AUX:ADC0.SMPL_MODE decides if the ADC trigger starts sampling or conversion.

adcfifostat: ADCFIFOSTAT

0x14 - ADC FIFO Status FIFO can hold up to four ADC samples.

adcfifo: ADCFIFO

0x18 - ADC FIFO

adctrig: ADCTRIG

0x1c - ADC Trigger

isrcctl: ISRCCTL

0x20 - Current Source Control

dacctl: DACCTL

0x30 - DAC Control This register controls the analog part of the DAC.

lpmbiasctl: LPMBIASCTL

0x34 - Low Power Mode Bias Control The low power mode bias module provides bias current to DAC and Comparator A when AUX_SYSIF:OPMODEREQ.REQ differers from A.

dacsmplctl: DACSMPLCTL

0x38 - DAC Sample Control The DAC sample clock maintains the DAC voltage stored in the sample-and-hold capacitor. The DAC sample clock waveform consists of a setup phase followed by a hold phase. In the setup phase the sample-and-hold capacitor charges to the programmed voltage. The hold phase maintains the voltage with minimal power. DACSMPLCFG0 and DACSMPLCFG1 configure the DAC sample clock waveform.

dacsmplcfg0: DACSMPLCFG0

0x3c - DAC Sample Configuration 0

dacsmplcfg1: DACSMPLCFG1

0x40 - DAC Sample Configuration 1 The sample clock period equals (high time + low time) * base period. DACSMPLCFG0.CLKDIV determines the base period. Timing requirements (DAC Buffer On / DAC Buffer Off): - (high time + low time) * base period > (4 us / 1 us) - (high time * base period) > (2 us / 0.5 us) - (low time * base period) > (2 us / 0.5 us) - (low time * base period + HOLD_INTERVAL * sample clock period) < 32 us If AUX_SYSIF:OPMODEREQ.REQ equals PDLP, you must set: - H_PER = L_PER = HOLD_INTERVAL = 0.

dacvalue: DACVALUE

0x44 - DAC Value

dacstat: DACSTAT

0x48 - DAC Status