[−][src]Module cc13x2_cc26x2_hal::uart0
Universal Asynchronous Receiver/Transmitter (UART) interface
Modules
ctl | Control |
dmactl | DMA Control |
dr | Data For words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: - if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from this register along with the corresponding status information. The status information can also be read by a read of the RSR register. |
ecr | Error Clear This register is mapped to the same address as RSR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). |
fbrd | Fractional Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete. |
fr | Flag Reads from this register return the UART flags. |
ibrd | Integer Baud-Rate Divisor If this register is modified while transmission or reception is on-going, the baud rate will not be updated until transmission or reception of the current character is complete. |
icr | Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. |
ifls | Interrupt FIFO Level Select |
imsc | Interrupt Mask Set/Clear |
lcrh | Line Control |
mis | Masked Interrupt Status |
reserved0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
reserved1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
reserved2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
reserved3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
reserved4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
ris | Raw Interrupt Status |
rsr | Status This register is mapped to the same address as ECR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register, DR prior to reading the RSR. The status information for overrun is set immediately when an overrun condition occurs. |
Structs
CTL | Control |
DMACTL | DMA Control |
DR | Data For words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1), data written to this location is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit (if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: - if the FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun) is pushed onto the 12-bit wide receive FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), the data byte and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received data byte is read by performing reads from this register along with the corresponding status information. The status information can also be read by a read of the RSR register. |
ECR | Error Clear This register is mapped to the same address as RSR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). |
FBRD | Fractional Baud-Rate Divisor If this register is modified while trasmission or reception is on-going, the baudrate will not be updated until transmission or reception of the current character is complete. |
FR | Flag Reads from this register return the UART flags. |
IBRD | Integer Baud-Rate Divisor If this register is modified while transmission or reception is on-going, the baud rate will not be updated until transmission or reception of the current character is complete. |
ICR | Interrupt Clear On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. |
IFLS | Interrupt FIFO Level Select |
IMSC | Interrupt Mask Set/Clear |
LCRH | Line Control |
MIS | Masked Interrupt Status |
RESERVED0 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RESERVED1 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RESERVED2 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RESERVED3 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RESERVED4 | Software should not rely on the value of a reserved. Writing any other value than the reset value may result in undefined behavior. |
RIS | Raw Interrupt Status |
RSR | Status This register is mapped to the same address as ECR register. Reads from this address are associated with RSR register and return the receive status. Writes to this address are associated with ECR register and clear the receive status flags (framing, parity, break, and overrun errors). If the status is read from this register, then the status information for break, framing and parity corresponds to the data character read from the Data Register, DR prior to reading the RSR. The status information for overrun is set immediately when an overrun condition occurs. |
RegisterBlock | Register block |