Module cc13x2_cc26x2_hal::cpu_scs::mpu_ctrl

MPU Control This register is used to enable the MPU, enable the default memory map (background region), and enable the MPU when in Hard Fault, Non-maskable Interrupt (NMI), and FAULTMASK escalated handlers. When the MPU is enabled, at least one region of the memory map must be enabled for the MPU to function unless the PRIVDEFENA bit is set. If the PRIVDEFENA bit is set and no regions are enabled, then only privileged code can operate. When the MPU is disabled, the default address map is used, as if no MPU is present. When the MPU is enabled, only the system partition and vector table loads are always accessible. Other areas are accessible based on regions and whether PRIVDEFENA is enabled. Unless HFNMIENA is set, the MPU is not enabled when the exception priority is -1 or -2. These priorities are only possible when in Hard fault, NMI, or when FAULTMASK is enabled. The HFNMIENA bit enables the MPU when operating with these two priorities.

Structs

ENABLER	Value of the field
HFNMIENAR	Value of the field
PRIVDEFENAR	Value of the field
R	Value read from the register
RESERVED3R	Value of the field
W	Value to write to the register
_ENABLEW	Proxy
_HFNMIENAW	Proxy
_PRIVDEFENAW	Proxy
_RESERVED3W	Proxy