//! The AVR ATtiny461A microcontroller
//!
//! # Variants
//! |        | Pinout | Mcuage | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 1.8V - 5.5V | 0 MHz |
//!

#![allow(non_upper_case_globals)]

/// LOW register
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | CKOUT | 1000000 |
/// | SUT_CKSEL | 111111 |
/// | CKDIV8 | 10000000 |
pub const LOW: *mut u8 = 0x0 as *mut u8;

/// LOCKBIT register
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | LB | 11 |
pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;

/// HIGH register
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | BODLEVEL | 111 |
/// | SPIEN | 100000 |
/// | WDTON | 10000 |
/// | EESAVE | 1000 |
/// | DWEN | 1000000 |
/// | RSTDISBL | 10000000 |
pub const HIGH: *mut u8 = 0x1 as *mut u8;

/// EXTENDED register
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | SELFPRGEN | 1 |
pub const EXTENDED: *mut u8 = 0x2 as *mut u8;

/// Timer/Counter1 Control Register E.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | OC1OE | 111111 |
pub const TCCR1E: *mut u8 = 0x20 as *mut u8;

/// Digital Input Disable Register 0.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ADC0D | 1 |
/// | ADC4D | 100000 |
/// | ADC6D | 10000000 |
/// | ADC1D | 10 |
/// | ADC5D | 1000000 |
/// | ADC2D | 100 |
/// | ADC3D | 10000 |
/// | AREFD | 1000 |
pub const DIDR0: *mut u8 = 0x21 as *mut u8;

/// Digital Input Disable Register 1.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ADC7D | 10000 |
/// | ADC10D | 10000000 |
/// | ADC9D | 1000000 |
/// | ADC8D | 100000 |
pub const DIDR1: *mut u8 = 0x22 as *mut u8;

/// ADC Control and Status Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | REFS2 | 10000 |
/// | BIN | 10000000 |
/// | IPR | 100000 |
/// | MUX5 | 1000 |
/// | ADTS | 111 |
/// | GSEL | 1000000 |
pub const ADCSRB: *mut u8 = 0x23 as *mut u8;

/// ADC Data Register  Bytes low byte.
pub const ADCL: *mut u8 = 0x24 as *mut u8;

/// ADC Data Register  Bytes.
pub const ADC: *mut u16 = 0x24 as *mut u16;

/// ADC Data Register  Bytes high byte.
pub const ADCH: *mut u8 = 0x25 as *mut u8;

/// The ADC Control and Status register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ADIF | 10000 |
/// | ADPS | 111 |
/// | ADIE | 1000 |
/// | ADEN | 10000000 |
/// | ADSC | 1000000 |
/// | ADATE | 100000 |
pub const ADCSRA: *mut u8 = 0x26 as *mut u8;

/// The ADC multiplexer Selection Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ADLAR | 100000 |
/// | REFS | 11000000 |
/// | MUX | 11111 |
pub const ADMUX: *mut u8 = 0x27 as *mut u8;

/// Analog Comparator Control And Status Register A.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ACO | 100000 |
/// | ACD | 10000000 |
/// | ACBG | 1000000 |
/// | ACIS | 11 |
/// | ACME | 100 |
/// | ACIE | 1000 |
/// | ACI | 10000 |
pub const ACSRA: *mut u8 = 0x28 as *mut u8;

/// Analog Comparator Control And Status Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | HLEV | 1000000 |
/// | HSEL | 10000000 |
/// | ACM | 111 |
pub const ACSRB: *mut u8 = 0x29 as *mut u8;

/// General purpose register 0.
pub const GPIOR0: *mut u8 = 0x2A as *mut u8;

/// General Purpose register 1.
pub const GPIOR1: *mut u8 = 0x2B as *mut u8;

/// General Purpose IO register 2.
pub const GPIOR2: *mut u8 = 0x2C as *mut u8;

/// USI Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | USIWM | 110000 |
/// | USITC | 1 |
/// | USICLK | 10 |
/// | USIOIE | 1000000 |
/// | USICS | 1100 |
/// | USISIE | 10000000 |
pub const USICR: *mut u8 = 0x2D as *mut u8;

/// USI Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | USISIF | 10000000 |
/// | USIDC | 10000 |
/// | USIPF | 100000 |
/// | USIOIF | 1000000 |
/// | USICNT | 1111 |
pub const USISR: *mut u8 = 0x2E as *mut u8;

/// USI Data Register.
pub const USIDR: *mut u8 = 0x2F as *mut u8;

/// USI Buffer Register.
pub const USIBR: *mut u8 = 0x30 as *mut u8;

/// USI Pin Position.
pub const USIPP: *mut u8 = 0x31 as *mut u8;

/// Timer/Counter0 Output Compare Register.
pub const OCR0B: *mut u8 = 0x32 as *mut u8;

/// Timer/Counter0 Output Compare Register.
pub const OCR0A: *mut u8 = 0x33 as *mut u8;

/// Timer/Counter0 High.
pub const TCNT0H: *mut u8 = 0x34 as *mut u8;

/// Timer/Counter  Control Register A.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ICES0 | 10000 |
/// | WGM00 | 1 |
/// | ACIC0 | 1000 |
/// | ICEN0 | 1000000 |
/// | ICNC0 | 100000 |
/// | TCW0 | 10000000 |
pub const TCCR0A: *mut u8 = 0x35 as *mut u8;

/// Port B Input Pins.
pub const PINB: *mut u8 = 0x36 as *mut u8;

/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x37 as *mut u8;

/// Port B Data Register.
pub const PORTB: *mut u8 = 0x38 as *mut u8;

/// Port A Input Pins.
pub const PINA: *mut u8 = 0x39 as *mut u8;

/// Port A Data Direction Register.
pub const DDRA: *mut u8 = 0x3A as *mut u8;

/// Port A Data Register.
pub const PORTA: *mut u8 = 0x3B as *mut u8;

/// EEPROM Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | EERIE | 1000 |
/// | EERE | 1 |
/// | EEPE | 10 |
/// | EEPM | 110000 |
/// | EEMPE | 100 |
pub const EECR: *mut u8 = 0x3C as *mut u8;

/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x3D as *mut u8;

/// EEPROM Address Register  Bytes low byte.
pub const EEARL: *mut u8 = 0x3E as *mut u8;

/// EEPROM Address Register  Bytes.
pub const EEAR: *mut u16 = 0x3E as *mut u16;

/// EEPROM Address Register  Bytes high byte.
pub const EEARH: *mut u8 = 0x3F as *mut u8;

/// debugWire data register.
pub const DWDR: *mut u8 = 0x40 as *mut u8;

/// Watchdog Timer Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | WDIE | 1000000 |
/// | WDP | 100111 |
/// | WDCE | 10000 |
/// | WDIF | 10000000 |
/// | WDE | 1000 |
pub const WDTCR: *mut u8 = 0x41 as *mut u8;

/// Pin Change Enable Mask 1.
pub const PCMSK1: *mut u8 = 0x42 as *mut u8;

/// Pin Change Enable Mask 0.
pub const PCMSK0: *mut u8 = 0x43 as *mut u8;

/// Timer/Counter 1 Dead Time Value.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | DT1H | 11110000 |
/// | DT1L | 1111 |
pub const DT1: *mut u8 = 0x44 as *mut u8;

/// Timer/Counter 1 Register High.
pub const TC1H: *mut u8 = 0x45 as *mut u8;

/// Timer/Counter Control Register D.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | WGM1 | 11 |
/// | FPIE1 | 10000000 |
/// | FPES1 | 10000 |
/// | FPF1 | 100 |
/// | FPAC1 | 1000 |
/// | FPNC1 | 100000 |
/// | FPEN1 | 1000000 |
pub const TCCR1D: *mut u8 = 0x46 as *mut u8;

/// Timer/Counter Control Register C.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | FOC1D | 10 |
/// | COM1A0S | 1000000 |
/// | COM1B1S | 100000 |
/// | COM1D | 1100 |
/// | PWM1D | 1 |
/// | COM1A1S | 10000000 |
/// | COM1B0S | 10000 |
pub const TCCR1C: *mut u8 = 0x47 as *mut u8;

/// Clock Prescale Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | CLKPS | 1111 |
/// | CLKPCE | 10000000 |
pub const CLKPR: *mut u8 = 0x48 as *mut u8;

/// PLL Control and status register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | PLLE | 10 |
/// | LSM | 10000000 |
/// | PLOCK | 1 |
/// | PCKE | 100 |
pub const PLLCSR: *mut u8 = 0x49 as *mut u8;

/// Output compare register.
pub const OCR1D: *mut u8 = 0x4A as *mut u8;

/// Output compare register.
pub const OCR1C: *mut u8 = 0x4B as *mut u8;

/// Output Compare Register.
pub const OCR1B: *mut u8 = 0x4C as *mut u8;

/// Output Compare Register.
pub const OCR1A: *mut u8 = 0x4D as *mut u8;

/// Timer/Counter Register.
pub const TCNT1: *mut u8 = 0x4E as *mut u8;

/// Timer/Counter Control Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | DTPS1 | 110000 |
/// | PSR1 | 1000000 |
/// | PWM1X | 10000000 |
/// | CS1 | 1111 |
pub const TCCR1B: *mut u8 = 0x4F as *mut u8;

/// Timer/Counter Control Register A.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | PWM1A | 10 |
/// | PWM1B | 1 |
/// | COM1B | 110000 |
/// | COM1A | 11000000 |
/// | FOC1A | 1000 |
/// | FOC1B | 100 |
pub const TCCR1A: *mut u8 = 0x50 as *mut u8;

/// Oscillator Calibration Register.
pub const OSCCAL: *mut u8 = 0x51 as *mut u8;

/// Timer/Counter0 Low.
pub const TCNT0L: *mut u8 = 0x52 as *mut u8;

/// Timer/Counter Control Register B.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TSM | 10000 |
/// | PSR0 | 1000 |
/// | CS0 | 111 |
pub const TCCR0B: *mut u8 = 0x53 as *mut u8;

/// MCU Status register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | EXTRF | 10 |
/// | PORF | 1 |
/// | WDRF | 1000 |
/// | BORF | 100 |
pub const MCUSR: *mut u8 = 0x54 as *mut u8;

/// MCU Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | ISC00 | 1 |
/// | ISC01 | 10 |
pub const MCUCR: *mut u8 = 0x55 as *mut u8;

/// Power Reduction Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | PRUSI | 10 |
/// | PRADC | 1 |
/// | PRTIM1 | 1000 |
/// | PRTIM0 | 100 |
pub const PRR: *mut u8 = 0x56 as *mut u8;

/// Store Program Memory Control Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | PGWRT | 100 |
/// | CTPB | 10000 |
/// | SPMEN | 1 |
/// | RFLB | 1000 |
/// | PGERS | 10 |
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;

/// Timer/Counter Interrupt Flag Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | TOV1 | 100 |
/// | OCF1D | 10000000 |
/// | OCF1A | 1000000 |
/// | OCF1B | 100000 |
pub const TIFR: *mut u8 = 0x58 as *mut u8;

/// Timer/Counter Interrupt Mask Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | OCIE1D | 10000000 |
/// | OCIE1A | 1000000 |
/// | OCIE1B | 100000 |
/// | TOIE1 | 100 |
pub const TIMSK: *mut u8 = 0x59 as *mut u8;

/// General Interrupt Flag register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | PCIF | 100000 |
/// | INTF | 11000000 |
pub const GIFR: *mut u8 = 0x5A as *mut u8;

/// General Interrupt Mask Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | INT | 11000000 |
/// | PCIE | 110000 |
pub const GIMSK: *mut u8 = 0x5B as *mut u8;

/// Stack Pointer  Bytes.
pub const SP: *mut u16 = 0x5D as *mut u16;

/// Stack Pointer  Bytes low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;

/// Stack Pointer  Bytes high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;

/// Status Register.
///
/// Bitfields:
///
/// | Name | Mask (binary) |
/// | ---- | ------------- |
/// | T | 1000000 |
/// | Z | 10 |
/// | I | 10000000 |
/// | N | 100 |
/// | H | 100000 |
/// | C | 1 |
/// | V | 1000 |
/// | S | 10000 |
pub const SREG: *mut u8 = 0x5F as *mut u8;

/// Bitfield on register ACSRA
pub const ACO: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register ACSRA
pub const ACD: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register ACSRA
pub const ACBG: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register ACSRA
pub const ACIS: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register ACSRA
pub const ACME: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register ACSRA
pub const ACIE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register ACSRA
pub const ACI: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register ACSRB
pub const HLEV: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register ACSRB
pub const HSEL: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register ACSRB
pub const ACM: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADIF: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADPS: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADIE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADEN: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADSC: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register ADCSRA
pub const ADATE: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register ADCSRB
pub const REFS2: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register ADCSRB
pub const BIN: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register ADCSRB
pub const IPR: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register ADCSRB
pub const MUX5: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register ADCSRB
pub const ADTS: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register ADCSRB
pub const GSEL: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register ADMUX
pub const ADLAR: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register ADMUX
pub const REFS: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register ADMUX
pub const MUX: *mut u8 = 0x1F as *mut u8;

/// Bitfield on register CLKPR
pub const CLKPS: *mut u8 = 0xF as *mut u8;

/// Bitfield on register CLKPR
pub const CLKPCE: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register DIDR0
pub const ADC0D: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register DIDR0
pub const ADC4D: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register DIDR0
pub const ADC6D: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register DIDR0
pub const ADC1D: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register DIDR0
pub const ADC5D: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register DIDR0
pub const ADC2D: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register DIDR0
pub const ADC3D: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register DIDR0
pub const AREFD: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register DIDR1
pub const ADC7D: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register DIDR1
pub const ADC10D: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register DIDR1
pub const ADC9D: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register DIDR1
pub const ADC8D: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register DT1
pub const DT1H: *mut u8 = 0xF0 as *mut u8;

/// Bitfield on register DT1
pub const DT1L: *mut u8 = 0xF as *mut u8;

/// Bitfield on register EECR
pub const EERIE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register EECR
pub const EERE: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register EECR
pub const EEPE: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register EECR
pub const EEPM: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register EECR
pub const EEMPE: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register EXTENDED
pub const SELFPRGEN: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register GIFR
pub const PCIF: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register GIFR
pub const INTF: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register GIMSK
pub const INT: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register GIMSK
pub const PCIE: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register HIGH
pub const BODLEVEL: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register HIGH
pub const SPIEN: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register HIGH
pub const WDTON: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register HIGH
pub const EESAVE: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register HIGH
pub const DWEN: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register HIGH
pub const RSTDISBL: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register LOCKBIT
pub const LB: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register LOW
pub const CKOUT: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register LOW
pub const SUT_CKSEL: *mut u8 = 0x3F as *mut u8;

/// Bitfield on register LOW
pub const CKDIV8: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register MCUCR
pub const ISC00: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register MCUCR
pub const ISC01: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register MCUSR
pub const EXTRF: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register MCUSR
pub const PORF: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register MCUSR
pub const WDRF: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register MCUSR
pub const BORF: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register PLLCSR
pub const PLLE: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register PLLCSR
pub const LSM: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register PLLCSR
pub const PLOCK: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register PLLCSR
pub const PCKE: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register PRR
pub const PRUSI: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register PRR
pub const PRADC: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register PRR
pub const PRTIM1: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register PRR
pub const PRTIM0: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register SPMCSR
pub const PGWRT: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register SPMCSR
pub const CTPB: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register SPMCSR
pub const SPMEN: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register SPMCSR
pub const RFLB: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register SPMCSR
pub const PGERS: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register SREG
pub const T: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register SREG
pub const Z: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register SREG
pub const I: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register SREG
pub const N: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register SREG
pub const H: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register SREG
pub const C: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register SREG
pub const V: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register SREG
pub const S: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register TCCR0A
pub const ICES0: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register TCCR0A
pub const WGM00: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register TCCR0A
pub const ACIC0: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register TCCR0A
pub const ICEN0: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TCCR0A
pub const ICNC0: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register TCCR0A
pub const TCW0: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TCCR0B
pub const TSM: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register TCCR0B
pub const PSR0: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register TCCR0B
pub const CS0: *mut u8 = 0x7 as *mut u8;

/// Bitfield on register TCCR1A
pub const PWM1A: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register TCCR1A
pub const PWM1B: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register TCCR1A
pub const COM1B: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register TCCR1A
pub const COM1A: *mut u8 = 0xC0 as *mut u8;

/// Bitfield on register TCCR1A
pub const FOC1A: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register TCCR1A
pub const FOC1B: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register TCCR1B
pub const DTPS1: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register TCCR1B
pub const PSR1: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TCCR1B
pub const PWM1X: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TCCR1B
pub const CS1: *mut u8 = 0xF as *mut u8;

/// Bitfield on register TCCR1C
pub const FOC1D: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register TCCR1C
pub const COM1A0S: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TCCR1C
pub const COM1B1S: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register TCCR1C
pub const COM1D: *mut u8 = 0xC as *mut u8;

/// Bitfield on register TCCR1C
pub const PWM1D: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register TCCR1C
pub const COM1A1S: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TCCR1C
pub const COM1B0S: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register TCCR1D
pub const WGM1: *mut u8 = 0x3 as *mut u8;

/// Bitfield on register TCCR1D
pub const FPIE1: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TCCR1D
pub const FPES1: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register TCCR1D
pub const FPF1: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register TCCR1D
pub const FPAC1: *mut u8 = 0x8 as *mut u8;

/// Bitfield on register TCCR1D
pub const FPNC1: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register TCCR1D
pub const FPEN1: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TCCR1E
pub const OC1OE: *mut u8 = 0x3F as *mut u8;

/// Bitfield on register TIFR
pub const TOV1: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register TIFR
pub const OCF1D: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TIFR
pub const OCF1A: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TIFR
pub const OCF1B: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register TIMSK
pub const OCIE1D: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register TIMSK
pub const OCIE1A: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register TIMSK
pub const OCIE1B: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register TIMSK
pub const TOIE1: *mut u8 = 0x4 as *mut u8;

/// Bitfield on register USICR
pub const USIWM: *mut u8 = 0x30 as *mut u8;

/// Bitfield on register USICR
pub const USITC: *mut u8 = 0x1 as *mut u8;

/// Bitfield on register USICR
pub const USICLK: *mut u8 = 0x2 as *mut u8;

/// Bitfield on register USICR
pub const USIOIE: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register USICR
pub const USICS: *mut u8 = 0xC as *mut u8;

/// Bitfield on register USICR
pub const USISIE: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register USISR
pub const USISIF: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register USISR
pub const USIDC: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register USISR
pub const USIPF: *mut u8 = 0x20 as *mut u8;

/// Bitfield on register USISR
pub const USIOIF: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register USISR
pub const USICNT: *mut u8 = 0xF as *mut u8;

/// Bitfield on register WDTCR
pub const WDIE: *mut u8 = 0x40 as *mut u8;

/// Bitfield on register WDTCR
pub const WDP: *mut u8 = 0x27 as *mut u8;

/// Bitfield on register WDTCR
pub const WDCE: *mut u8 = 0x10 as *mut u8;

/// Bitfield on register WDTCR
pub const WDIF: *mut u8 = 0x80 as *mut u8;

/// Bitfield on register WDTCR
pub const WDE: *mut u8 = 0x8 as *mut u8;