//! The AVR ATxmega32E5 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | ATxmega32E5-AU | QFP_QFN_32 | TQFP32 | -40°C - 85°C | 1.6V - 3.6V | 32 MHz |
//! | ATxmega32E5-MU | QFP_QFN_32 | VQFN32 | -40°C - 85°C | 1.6V - 3.6V | 32 MHz |
//! | ATxmega32E5-M4U | QFP_QFN_32 | UQFN32 | -40°C - 85°C | 1.6V - 3.6V | 32 MHz |
//! | ATxmega32E5-AN | QFP_QFN_32 | TQFP32 | -40°C - 105°C | 1.6V - 3.6V | 32 MHz |
//! | ATxmega32E5-MN | QFP_QFN_32 | VQFN32 | -40°C - 105°C | 1.6V - 3.6V | 32 MHz |
//! | ATxmega32E5-M4N | QFP_QFN_32 | UQFN32 | -40°C - 105°C | 1.6V - 3.6V | 32 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTA
//!     * PA0 (PA0)
//!     * PA1 (PA1)
//!     * PA2 (PA2)
//!     * PA3 (PA3)
//!     * PA4 (PA4)
//!     * PA5 (PA5)
//!     * PA6 (PA6)
//!     * PA7 (PA7)
//! * PORTC
//!     * PC0 (PC0)
//!     * PC1 (PC1)
//!     * PC2 (PC2)
//!     * PC3 (PC3)
//!     * PC4 (PC4)
//!     * PC5 (PC5)
//!     * PC6 (PC6)
//!     * PC7 (PC7)
//! * PORTD
//!     * PD0 (PD0)
//!     * PD1 (PD1)
//!     * PD2 (PD2)
//!     * PD3 (PD3)
//!     * PD4 (PD4)
//!     * PD5 (PD5)
//!     * PD6 (PD6)
//!     * PD7 (PD7)
//! * PORTR
//!     * PR0 (PR0)
//!     * PR1 (PR1)
//!
//! ## ADC modules
//!
//! * ADCA
//!     * PA0 (PA0)
//!     * PA1 (PA1)
//!     * PA2 (PA2)
//!     * PA3 (PA3)
//!     * PA4 (PA4)
//!     * PA5 (PA5)
//!     * PA6 (PA6)
//!     * PA7 (PA7)
//!     * PD0 (PD0)
//!     * PD1 (PD1)
//!     * PD2 (PD2)
//!     * PD3 (PD3)
//!     * PD4 (PD4)
//!     * PD5 (PD5)
//!     * PD6 (PD6)
//!     * PD7 (PD7)
//!     * PA0 (PA0)
//!     * PD0 (PD0)
//!
//! ## USART modules
//!
//! * USARTC0
//!     * PC1 (PC1)
//!     * PC2 (PC2)
//!     * PC3 (PC3)
//!     * PC5 (PC5)
//!     * PC6 (PC6)
//!     * PC7 (PC7)
//! * USARTD0
//!     * PD1 (PD1)
//!     * PD2 (PD2)
//!     * PD3 (PD3)
//!     * PD5 (PD5)
//!     * PD6 (PD6)
//!     * PD7 (PD7)

/// OCD Register 0.
pub const OCDR0: *mut u8 = 0x0 as *mut u8;
/// Lock Bits.
pub const LOCKBITS: *mut u8 = 0x0 as *mut u8;
/// Device ID byte 0.
pub const DEVID0: *mut u8 = 0x0 as *mut u8;
/// General Power Reduction.
pub const PRGEN: *mut u8 = 0x0 as *mut u8;
/// Control Register.
pub const CTRL: *mut u8 = 0x0 as *mut u8;
/// RCOSC 8MHz Calibration Value.
pub const RCOSC8M: *mut u8 = 0x0 as *mut u8;
/// Analog Comparator 0 Control.
pub const AC0CTRL: *mut u8 = 0x0 as *mut u8;
/// Timeout Status Register.
pub const TOS: *mut u8 = 0x0 as *mut u8;
/// Address Register 0.
pub const ADDR0: *mut u8 = 0x0 as *mut u8;
/// I/O Port Data Direction.
pub const DIR: *mut u8 = 0x0 as *mut u8;
/// Event Channel 0 Multiplexer.
pub const CH0MUX: *mut u8 = 0x0 as *mut u8;
/// General Purpose IO Register 0.
pub const GPIOR0: *mut u8 = 0x0 as *mut u8;
/// Multi-pin Configuration Mask.
pub const MPCMASK: *mut u8 = 0x0 as *mut u8;
/// Event Channel 1 Multiplexer.
pub const CH1MUX: *mut u8 = 0x1 as *mut u8;
/// OCD Register 1.
pub const OCDR1: *mut u8 = 0x1 as *mut u8;
/// General Purpose IO Register 1.
pub const GPIOR1: *mut u8 = 0x1 as *mut u8;
/// Address Register 1.
pub const ADDR1: *mut u8 = 0x1 as *mut u8;
/// Prescaler Control Register.
pub const PSCTRL: *mut u8 = 0x1 as *mut u8;
/// Timeout Configuration Register.
pub const TOCONF: *mut u8 = 0x1 as *mut u8;
/// Dead-time Concurrent Write to Both Sides Register.
pub const DTBOTH: *mut u8 = 0x1 as *mut u8;
/// Device ID byte 1.
pub const DEVID1: *mut u8 = 0x1 as *mut u8;
/// I/O Port Data Direction Set.
pub const DIRSET: *mut u8 = 0x1 as *mut u8;
/// IrDA Transmitter Pulse Length Control Register.
pub const TXPLCTRL: *mut u8 = 0x1 as *mut u8;
/// Interrupt Priority.
pub const INTPRI: *mut u8 = 0x1 as *mut u8;
/// Power Reduction Port A.
pub const PRPA: *mut u8 = 0x1 as *mut u8;
/// MUX Control.
pub const MUXCTRL: *mut u8 = 0x1 as *mut u8;
/// Analog Comparator 1 Control.
pub const AC1CTRL: *mut u8 = 0x1 as *mut u8;
/// Watchdog Configuration.
pub const FUSEBYTE1: *mut u8 = 0x1 as *mut u8;
/// Interrupt Control Register.
pub const INTCTRL: *mut u8 = 0x1 as *mut u8;
/// Lock register.
pub const LOCK: *mut u8 = 0x2 as *mut u8;
/// RCOSC 32.768 kHz Calibration Value.
pub const RCOSC32K: *mut u8 = 0x2 as *mut u8;
/// I/O Port Data Direction Clear.
pub const DIRCLR: *mut u8 = 0x2 as *mut u8;
/// Dead-time Low Side Register.
pub const DTLS: *mut u8 = 0x2 as *mut u8;
/// Memory Address Control for Peripheral Ch., or Source Address Control for Standard Ch.
pub const ADDRCTRL: *mut u8 = 0x2 as *mut u8;
/// Calibration Register A.
pub const CALA: *mut u8 = 0x2 as *mut u8;
/// Analog Comparator 0 MUX Control.
pub const AC0MUXCTRL: *mut u8 = 0x2 as *mut u8;
/// Reference Control.
pub const REFCTRL: *mut u8 = 0x2 as *mut u8;
/// Control Register A.
pub const CTRLA: *mut u8 = 0x2 as *mut u8;
/// External Oscillator Control Register.
pub const XOSCCTRL: *mut u8 = 0x2 as *mut u8;
/// Reset Configuration.
pub const FUSEBYTE2: *mut u8 = 0x2 as *mut u8;
/// Status Register.
pub const STATUS: *mut u8 = 0x2 as *mut u8;
/// Device ID byte 2.
pub const DEVID2: *mut u8 = 0x2 as *mut u8;
/// Address Register 2.
pub const ADDR2: *mut u8 = 0x2 as *mut u8;
/// IrDA Receiver Pulse Length Control Register.
pub const RXPLCTRL: *mut u8 = 0x2 as *mut u8;
/// Event Channel 2 Multiplexer.
pub const CH2MUX: *mut u8 = 0x2 as *mut u8;
/// General Purpose IO Register 2.
pub const GPIOR2: *mut u8 = 0x2 as *mut u8;
/// Data Input.
pub const DATAIN: *mut u8 = 0x3 as *mut u8;
/// Calibration Register B.
pub const CALB: *mut u8 = 0x3 as *mut u8;
/// General Purpose IO Register 3.
pub const GPIOR3: *mut u8 = 0x3 as *mut u8;
/// Event Input Control.
pub const EVCTRL: *mut u8 = 0x3 as *mut u8;
/// Event Channel 3 Multiplexer.
pub const CH3MUX: *mut u8 = 0x3 as *mut u8;
/// Revision ID.
pub const REVID: *mut u8 = 0x3 as *mut u8;
/// Analog Comparator 1 MUX Control.
pub const AC1MUXCTRL: *mut u8 = 0x3 as *mut u8;
/// Data Register.
pub const DATA: *mut u8 = 0x3 as *mut u8;
/// I/O Port Data Direction Toggle.
pub const DIRTGL: *mut u8 = 0x3 as *mut u8;
/// Address Register.
pub const ADDR: *mut u8 = 0x3 as *mut u8;
/// RCOSC 32 MHz Calibration Value B.
pub const RCOSC32M: *mut u8 = 0x3 as *mut u8;
/// Power Reduction Port C.
pub const PRPC: *mut u8 = 0x3 as *mut u8;
/// Destination Address Control for Standard Channels Only.
pub const DESTADDRCTRL: *mut u8 = 0x3 as *mut u8;
/// Dead-time High Side Register.
pub const DTHS: *mut u8 = 0x3 as *mut u8;
/// Oscillator Failure Detection Register.
pub const XOSCFAIL: *mut u8 = 0x3 as *mut u8;
/// RTC Control Register.
pub const RTCCTRL: *mut u8 = 0x3 as *mut u8;
/// Clock Out Register.
pub const CLKOUT: *mut u8 = 0x4 as *mut u8;
/// Clock Prescaler.
pub const PRESCALER: *mut u8 = 0x4 as *mut u8;
/// I/O Port Output.
pub const OUT: *mut u8 = 0x4 as *mut u8;
/// Data Register 0.
pub const DATA0: *mut u8 = 0x4 as *mut u8;
/// Event Channel 4 Multiplexer.
pub const CH4MUX: *mut u8 = 0x4 as *mut u8;
/// Power Reduction Port D.
pub const PRPD: *mut u8 = 0x4 as *mut u8;
/// Configuration Change Protection.
pub const CCP: *mut u8 = 0x4 as *mut u8;
/// Checksum byte 0.
pub const CHECKSUM0: *mut u8 = 0x4 as *mut u8;
/// RCOSC 32 MHz Calibration Value A.
pub const RCOSC32MA: *mut u8 = 0x4 as *mut u8;
/// Control Register B.
pub const CTRLB: *mut u8 = 0x4 as *mut u8;
/// 32.768 kHz Internal Oscillator Calibration Register.
pub const RC32KCAL: *mut u8 = 0x4 as *mut u8;
/// Channel Trigger Source.
pub const TRIGSRC: *mut u8 = 0x4 as *mut u8;
/// Channel Result.
pub const RES: *mut u16 = 0x4 as *mut u16;
/// Start-up Configuration.
pub const FUSEBYTE4: *mut u8 = 0x4 as *mut u8;
/// Status Clear Register.
pub const STATUSCLR: *mut u8 = 0x4 as *mut u8;
/// Oscillator Compare Register 0.
pub const COMP0: *mut u8 = 0x4 as *mut u8;
/// Baurd Rate Control Register.
pub const BAUD: *mut u8 = 0x4 as *mut u8;
/// Control Register C.
pub const CTRLC: *mut u8 = 0x4 as *mut u8;
/// Channel Result low byte.
pub const RESL: *mut u8 = 0x4 as *mut u8;
/// Control E Register.
pub const CTRLE: *mut u8 = 0x4 as *mut u8;
/// Channel Result high byte.
pub const RESH: *mut u8 = 0x5 as *mut u8;
/// Data Register 1.
pub const DATA1: *mut u8 = 0x5 as *mut u8;
/// Address Mask Register.
pub const ADDRMASK: *mut u8 = 0x5 as *mut u8;
/// Event Channel 5 Multiplexer.
pub const CH5MUX: *mut u8 = 0x5 as *mut u8;
/// PLL Control Register.
pub const PLLCTRL: *mut u8 = 0x5 as *mut u8;
/// Control Register F.
pub const CTRLF: *mut u8 = 0x5 as *mut u8;
/// Checksum byte 1.
pub const CHECKSUM1: *mut u8 = 0x5 as *mut u8;
/// EESAVE and BOD Level.
pub const FUSEBYTE5: *mut u8 = 0x5 as *mut u8;
/// Control Register D.
pub const CTRLD: *mut u8 = 0x5 as *mut u8;
/// Status Set Register.
pub const STATUSSET: *mut u8 = 0x5 as *mut u8;
/// I/O Port Output Set.
pub const OUTSET: *mut u8 = 0x5 as *mut u8;
/// Oscillator Compare Register 1.
pub const COMP1: *mut u8 = 0x5 as *mut u8;
/// Window Mode Control.
pub const WINCTRL: *mut u8 = 0x6 as *mut u8;
/// Swap Register.
pub const SWAP: *mut u8 = 0x6 as *mut u8;
/// Oscillator Compare Register 2.
pub const COMP2: *mut u8 = 0x6 as *mut u8;
/// I/O Port Output Clear.
pub const OUTCLR: *mut u8 = 0x6 as *mut u8;
/// DFLL Control Register.
pub const DFLLCTRL: *mut u8 = 0x6 as *mut u8;
/// Control Register G Clear.
pub const CTRLGCLR: *mut u8 = 0x6 as *mut u8;
/// Fault State.
pub const FUSEBYTE6: *mut u8 = 0x6 as *mut u8;
/// Baud Rate Control Register A.
pub const BAUDCTRLA: *mut u8 = 0x6 as *mut u8;
/// Event Channel 6 Multiplexer.
pub const CH6MUX: *mut u8 = 0x6 as *mut u8;
/// Control Register G.
pub const CTRLG: *mut u8 = 0x6 as *mut u8;
/// Input Channel Scan.
pub const SCAN: *mut u8 = 0x6 as *mut u8;
/// Calibration Register.
pub const CALIB: *mut u8 = 0x6 as *mut u8;
/// Interrupt Control Register A.
pub const INTCTRLA: *mut u8 = 0x6 as *mut u8;
/// Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. low byte.
pub const TRFCNTL: *mut u8 = 0x6 as *mut u8;
/// Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch.
pub const TRFCNT: *mut u16 = 0x6 as *mut u16;
/// Checksum byte 2.
pub const CHECKSUM2: *mut u8 = 0x6 as *mut u8;
/// Data Register 2.
pub const DATA2: *mut u8 = 0x6 as *mut u8;
/// Analog Comparator and Event Out Register.
pub const ACEVOUT: *mut u8 = 0x6 as *mut u8;
/// Internal 8 MHz RC Oscillator Calibration Register.
pub const RC8MCAL: *mut u8 = 0x7 as *mut u8;
/// Interrupt Control Register B.
pub const INTCTRLB: *mut u8 = 0x7 as *mut u8;
/// Pattern Generation Override Register.
pub const PGO: *mut u8 = 0x7 as *mut u8;
/// Checksum byte 3.
pub const CHECKSUM3: *mut u8 = 0x7 as *mut u8;
/// Analog Startup Delay.
pub const ANAINIT: *mut u8 = 0x7 as *mut u8;
/// Channel Block Transfer Count for Peripheral Ch., or Channel Block Transfer Count Low for Standard Ch. high byte.
pub const TRFCNTH: *mut u8 = 0x7 as *mut u8;
/// Correction Control Register.
pub const CORRCTRL: *mut u8 = 0x7 as *mut u8;
/// Event Channel 7 Multiplexer.
pub const CH7MUX: *mut u8 = 0x7 as *mut u8;
/// Control Register G set.
pub const CTRLGSET: *mut u8 = 0x7 as *mut u8;
/// Slew Rate Limit Control Register.
pub const SRLCTRL: *mut u8 = 0x7 as *mut u8;
/// Baud Rate Control Register B.
pub const BAUDCTRLB: *mut u8 = 0x7 as *mut u8;
/// I/O Port Output Toggle.
pub const OUTTGL: *mut u8 = 0x7 as *mut u8;
/// Channel 0 Control Register.
pub const CH0CTRL: *mut u8 = 0x8 as *mut u8;
/// Current Source Control Register.
pub const CURRCTRL: *mut u8 = 0x8 as *mut u8;
/// Gain Calibration.
pub const CH0GAINCAL: *mut u8 = 0x8 as *mut u8;
/// ADC Sampling Time Control Register.
pub const SAMPCTRL: *mut u8 = 0x8 as *mut u8;
/// Offset Correction Register 0.
pub const OFFSETCORR0: *mut u8 = 0x8 as *mut u8;
/// Pattern Generation Value Register.
pub const PGV: *mut u8 = 0x8 as *mut u8;
/// I/O port Input.
pub const IN: *mut u8 = 0x8 as *mut u8;
/// Ramp D.
pub const RAMPD: *mut u8 = 0x8 as *mut u8;
/// Lot Number Byte 0, ASCII.
pub const LOTNUM0: *mut u8 = 0x8 as *mut u8;
/// Event System Lock.
pub const EVSYSLOCK: *mut u8 = 0x8 as *mut u8;
/// Offset Calibration.
pub const CH0OFFSETCAL: *mut u8 = 0x9 as *mut u8;
/// Offset Correction Register 1.
pub const OFFSETCORR1: *mut u8 = 0x9 as *mut u8;
/// Current Source Calibration Register.
pub const CURRCALIB: *mut u8 = 0x9 as *mut u8;
/// Peripheral Lenght Control Register.
pub const PLC: *mut u8 = 0x9 as *mut u8;
/// Ramp X.
pub const RAMPX: *mut u8 = 0x9 as *mut u8;
/// WEX Lock.
pub const WEXLOCK: *mut u8 = 0x9 as *mut u8;
/// Lot Number Byte 1, ASCII.
pub const LOTNUM1: *mut u8 = 0x9 as *mut u8;
/// Channel 1 Control Register.
pub const CH1CTRL: *mut u8 = 0x9 as *mut u8;
/// Gain Calibration.
pub const CH1GAINCAL: *mut u8 = 0xA as *mut u8;
/// Control Register H Clear.
pub const CTRLHCLR: *mut u8 = 0xA as *mut u8;
/// FAULT Lock.
pub const FAULTLOCK: *mut u8 = 0xA as *mut u8;
/// Channel 2 Control Register.
pub const CH2CTRL: *mut u8 = 0xA as *mut u8;
/// Port Interrupt Mask.
pub const INTMASK: *mut u8 = 0xA as *mut u8;
/// Gain Correction Register 0.
pub const GAINCORR0: *mut u8 = 0xA as *mut u8;
/// Command.
pub const CMD: *mut u8 = 0xA as *mut u8;
/// Lot Number Byte 2, ASCII.
pub const LOTNUM2: *mut u8 = 0xA as *mut u8;
/// Counter Register Low.
pub const CNTL: *mut u8 = 0xA as *mut u8;
/// Ramp Y.
pub const RAMPY: *mut u8 = 0xA as *mut u8;
/// Dead Time Low Side Buffer.
pub const SWAPBUF: *mut u8 = 0xA as *mut u8;
/// Lot Number Byte 3, ASCII.
pub const LOTNUM3: *mut u8 = 0xB as *mut u8;
/// Offset Calibration.
pub const CH1OFFSETCAL: *mut u8 = 0xB as *mut u8;
/// Ramp Z.
pub const RAMPZ: *mut u8 = 0xB as *mut u8;
/// Control Register H Set.
pub const CTRLHSET: *mut u8 = 0xB as *mut u8;
/// Gain Correction Register 1.
pub const GAINCORR1: *mut u8 = 0xB as *mut u8;
/// Pattern Generation Overwrite Buffer Register.
pub const PGOBUF: *mut u8 = 0xB as *mut u8;
/// Counter Register High.
pub const CNTH: *mut u8 = 0xB as *mut u8;
/// Channel 3 Control Register.
pub const CH3CTRL: *mut u8 = 0xB as *mut u8;
/// Compare Register low byte.
pub const COMPL: *mut u8 = 0xC as *mut u8;
/// Extended Indirect Jump.
pub const EIND: *mut u8 = 0xC as *mut u8;
/// Pattern Generation Value Buffer Register.
pub const PGVBUF: *mut u8 = 0xC as *mut u8;
/// Channel 4 Control Register.
pub const CH4CTRL: *mut u8 = 0xC as *mut u8;
/// Compare Register Low.
pub const CMPL: *mut u8 = 0xC as *mut u8;
/// Compare Register.
pub const COMP: *mut u16 = 0xC as *mut u16;
/// Channel Destination Address for Standard Channels Only.
pub const DESTADDR: *mut u16 = 0xC as *mut u16;
/// Average Control Register.
pub const AVGCTRL: *mut u8 = 0xC as *mut u8;
/// Channel Destination Address for Standard Channels Only. low byte.
pub const DESTADDRL: *mut u8 = 0xC as *mut u8;
/// Calibration Value.
pub const CAL: *mut u8 = 0xC as *mut u8;
/// Interrupt Flag Register.
pub const INTFLAGS: *mut u8 = 0xC as *mut u8;
/// Lot Number Byte 4, ASCII.
pub const LOTNUM4: *mut u8 = 0xC as *mut u8;
/// Stack Pointer Low.
pub const SPL: *mut u8 = 0xD as *mut u8;
/// Compare Register high byte.
pub const COMPH: *mut u8 = 0xD as *mut u8;
/// Compare Register High.
pub const CMPH: *mut u8 = 0xD as *mut u8;
/// Channel Destination Address for Standard Channels Only. high byte.
pub const DESTADDRH: *mut u8 = 0xD as *mut u8;
/// Channel 5 Control Register.
pub const CH5CTRL: *mut u8 = 0xD as *mut u8;
/// Lot Number Byte 5, ASCII.
pub const LOTNUM5: *mut u8 = 0xD as *mut u8;
/// Stack Pointer High.
pub const SPH: *mut u8 = 0xE as *mut u8;
/// Channel 6 Control Register.
pub const CH6CTRL: *mut u8 = 0xE as *mut u8;
/// Period or Capture Register Low.
pub const PERCAPTL: *mut u8 = 0xE as *mut u8;
/// Pin Remap Register.
pub const REMAP: *mut u8 = 0xE as *mut u8;
/// Period or Capture Register High.
pub const PERCAPTH: *mut u8 = 0xF as *mut u8;
/// Temporary Register For 16-bit Access.
pub const TEMP: *mut u8 = 0xF as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0xF as *mut u8;
/// Output Override Disable Register.
pub const OUTOVDIS: *mut u8 = 0xF as *mut u8;
/// Channel 7 Control Register.
pub const CH7CTRL: *mut u8 = 0xF as *mut u8;
/// Pin 0 Control Register.
pub const PIN0CTRL: *mut u8 = 0x10 as *mut u8;
/// Channel 0 Result low byte.
pub const CH0RESL: *mut u8 = 0x10 as *mut u8;
/// Channel 0 Result.
pub const CH0RES: *mut u16 = 0x10 as *mut u16;
/// Wafer Number.
pub const WAFNUM: *mut u8 = 0x10 as *mut u8;
/// Event Strobe.
pub const STROBE: *mut u8 = 0x10 as *mut u8;
/// Channel 0 Result high byte.
pub const CH0RESH: *mut u8 = 0x11 as *mut u8;
/// Pin 1 Control Register.
pub const PIN1CTRL: *mut u8 = 0x11 as *mut u8;
/// Wafer Coordinate X Byte 0.
pub const COORDX0: *mut u8 = 0x12 as *mut u8;
/// Digital Filter Control Register.
pub const DFCTRL: *mut u8 = 0x12 as *mut u8;
/// Pin 2 Control Register.
pub const PIN2CTRL: *mut u8 = 0x12 as *mut u8;
/// Wafer Coordinate X Byte 1.
pub const COORDX1: *mut u8 = 0x13 as *mut u8;
/// Pin 3 Control Register.
pub const PIN3CTRL: *mut u8 = 0x13 as *mut u8;
/// Wafer Coordinate Y Byte 0.
pub const COORDY0: *mut u8 = 0x14 as *mut u8;
/// Pin 4 Control Register.
pub const PIN4CTRL: *mut u8 = 0x14 as *mut u8;
/// Wafer Coordinate Y Byte 1.
pub const COORDY1: *mut u8 = 0x15 as *mut u8;
/// Pin 5 Control Register.
pub const PIN5CTRL: *mut u8 = 0x15 as *mut u8;
/// Pin 6 Control Register.
pub const PIN6CTRL: *mut u8 = 0x16 as *mut u8;
/// Pin 7 Control Register.
pub const PIN7CTRL: *mut u8 = 0x17 as *mut u8;
/// Channel 0 Data.
pub const CH0DATA: *mut u16 = 0x18 as *mut u16;
/// Compare Value.
pub const CMP: *mut u16 = 0x18 as *mut u16;
/// Channel 0 Data low byte.
pub const CH0DATAL: *mut u8 = 0x18 as *mut u8;
/// Channel 0 Data high byte.
pub const CH0DATAH: *mut u8 = 0x19 as *mut u8;
/// Channel 1 Data low byte.
pub const CH1DATAL: *mut u8 = 0x1A as *mut u8;
/// Channel 1 Data.
pub const CH1DATA: *mut u16 = 0x1A as *mut u16;
/// Channel 1 Data high byte.
pub const CH1DATAH: *mut u8 = 0x1B as *mut u8;
/// Temperature corresponds to TEMPSENSE3/2.
pub const ROOMTEMP: *mut u8 = 0x1E as *mut u8;
/// Temperature corresponds to TEMPSENSE1/0.
pub const HOTTEMP: *mut u8 = 0x1F as *mut u8;
/// Count.
pub const CNT: *mut u16 = 0x20 as *mut u16;
/// ADCA Calibration Byte 0.
pub const ADCACAL0: *mut u8 = 0x20 as *mut u8;
/// ADCA Calibration Byte 1.
pub const ADCACAL1: *mut u8 = 0x21 as *mut u8;
/// Period low byte.
pub const PERL: *mut u8 = 0x26 as *mut u8;
/// Period.
pub const PER: *mut u16 = 0x26 as *mut u16;
/// Period high byte.
pub const PERH: *mut u8 = 0x27 as *mut u8;
/// Compare or Capture A.
pub const CCA: *mut u16 = 0x28 as *mut u16;
/// ACA Current Calibration Byte.
pub const ACACURRCAL: *mut u8 = 0x28 as *mut u8;
/// Compare or Capture A low byte.
pub const CCAL: *mut u8 = 0x28 as *mut u8;
/// Compare or Capture A high byte.
pub const CCAH: *mut u8 = 0x29 as *mut u8;
/// Compare or Capture B.
pub const CCB: *mut u16 = 0x2A as *mut u16;
/// Compare or Capture B low byte.
pub const CCBL: *mut u8 = 0x2A as *mut u8;
/// Compare or Capture B high byte.
pub const CCBH: *mut u8 = 0x2B as *mut u8;
/// Temperature Sensor Calibration Byte 2.
pub const TEMPSENSE2: *mut u8 = 0x2C as *mut u8;
/// Compare or Capture C low byte.
pub const CCCL: *mut u8 = 0x2C as *mut u8;
/// Compare or Capture C.
pub const CCC: *mut u16 = 0x2C as *mut u16;
/// Temperature Sensor Calibration Byte 3.
pub const TEMPSENSE3: *mut u8 = 0x2D as *mut u8;
/// Compare or Capture C high byte.
pub const CCCH: *mut u8 = 0x2D as *mut u8;
/// Compare or Capture D low byte.
pub const CCDL: *mut u8 = 0x2E as *mut u8;
/// Compare or Capture D.
pub const CCD: *mut u16 = 0x2E as *mut u16;
/// Temperature Sensor Calibration Byte 0.
pub const TEMPSENSE0: *mut u8 = 0x2E as *mut u8;
/// Compare or Capture D high byte.
pub const CCDH: *mut u8 = 0x2F as *mut u8;
/// Temperature Sensor Calibration Byte 1.
pub const TEMPSENSE1: *mut u8 = 0x2F as *mut u8;
/// DACA0 Calibration Byte 0.
pub const DACA0OFFCAL: *mut u8 = 0x30 as *mut u8;
/// DACA0 Calibration Byte 1.
pub const DACA0GAINCAL: *mut u8 = 0x31 as *mut u8;
/// DACA1 Calibration Byte 0.
pub const DACA1OFFCAL: *mut u8 = 0x34 as *mut u8;
/// DACA1 Calibration Byte 1.
pub const DACA1GAINCAL: *mut u8 = 0x35 as *mut u8;
/// Period Buffer low byte.
pub const PERBUFL: *mut u8 = 0x36 as *mut u8;
/// Period Buffer.
pub const PERBUF: *mut u16 = 0x36 as *mut u16;
/// Period Buffer high byte.
pub const PERBUFH: *mut u8 = 0x37 as *mut u8;
/// Compare Or Capture A Buffer low byte.
pub const CCABUFL: *mut u8 = 0x38 as *mut u8;
/// Compare Or Capture A Buffer.
pub const CCABUF: *mut u16 = 0x38 as *mut u16;
/// Compare Or Capture A Buffer high byte.
pub const CCABUFH: *mut u8 = 0x39 as *mut u8;
/// Compare Or Capture B Buffer.
pub const CCBBUF: *mut u16 = 0x3A as *mut u16;
/// Compare Or Capture B Buffer low byte.
pub const CCBBUFL: *mut u8 = 0x3A as *mut u8;
/// Compare Or Capture B Buffer high byte.
pub const CCBBUFH: *mut u8 = 0x3B as *mut u8;
/// Compare Or Capture C Buffer.
pub const CCCBUF: *mut u16 = 0x3C as *mut u16;
/// Compare Or Capture C Buffer low byte.
pub const CCCBUFL: *mut u8 = 0x3C as *mut u8;
/// Compare Or Capture C Buffer high byte.
pub const CCCBUFH: *mut u8 = 0x3D as *mut u8;
/// Compare Or Capture D Buffer.
pub const CCDBUF: *mut u16 = 0x3E as *mut u16;
/// Compare Or Capture D Buffer low byte.
pub const CCDBUFL: *mut u8 = 0x3E as *mut u8;
/// Compare Or Capture D Buffer high byte.
pub const CCDBUFH: *mut u8 = 0x3F as *mut u8;