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//! The AVR AT90PWM81 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | standard |  |  | 0°C - 0°C | 2.7V - 5.5V | 0 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTB
//! * PORTD
//! * PORTE
//!
//! ## ADC modules
//!
//! * ADC
//!
//! ## EEPROM modules
//!
//! * EEPROM

pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const HIGH: *mut u8 = 0x1 as *mut u8;
pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
/// Analog Comparator Status Register.
pub const ACSR: *mut u8 = 0x20 as *mut u8;
/// Timer/Counter Interrupt Mask Register.
pub const TIMSK1: *mut u8 = 0x21 as *mut u8;
/// Timer/Counter Interrupt Flag register.
pub const TIFR1: *mut u8 = 0x22 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x23 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x24 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x25 as *mut u8;
/// The ADC Control and Status register.
pub const ADCSRA: *mut u8 = 0x26 as *mut u8;
/// ADC Control and Status Register B.
pub const ADCSRB: *mut u8 = 0x27 as *mut u8;
/// The ADC multiplexer Selection Register.
pub const ADMUX: *mut u8 = 0x28 as *mut u8;
/// Port D Input Pins.
pub const PIND: *mut u8 = 0x29 as *mut u8;
/// Port D Data Direction Register.
pub const DDRD: *mut u8 = 0x2A as *mut u8;
/// Port D Data Register.
pub const PORTD: *mut u8 = 0x2B as *mut u8;
/// Port E Input Pins.
pub const PINE: *mut u8 = 0x2C as *mut u8;
/// Port E Data Direction Register.
pub const DDRE: *mut u8 = 0x2D as *mut u8;
/// Port E Data Register.
pub const PORTE: *mut u8 = 0x2E as *mut u8;
/// PSC0 Interrupt Mask Register.
pub const PIM0: *mut u8 = 0x2F as *mut u8;
/// PSC0 Interrupt Flag Register.
pub const PIFR0: *mut u8 = 0x30 as *mut u8;
/// PSC 0 Configuration Register.
pub const PCNF0: *mut u8 = 0x31 as *mut u8;
/// PSC 0 Control Register.
pub const PCTL0: *mut u8 = 0x32 as *mut u8;
/// PSC2 Interrupt Mask Register.
pub const PIM2: *mut u8 = 0x33 as *mut u8;
/// PSC2 Interrupt Flag Register.
pub const PIFR2: *mut u8 = 0x34 as *mut u8;
/// PSC 2 Configuration Register.
pub const PCNF2: *mut u8 = 0x35 as *mut u8;
/// PSC 2 Control Register.
pub const PCTL2: *mut u8 = 0x36 as *mut u8;
/// SPI Control Register.
pub const SPCR: *mut u8 = 0x37 as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0x38 as *mut u8;
/// General Purpose IO Register 0.
pub const GPIOR0: *mut u8 = 0x39 as *mut u8;
/// General Purpose IO Register 1.
pub const GPIOR1: *mut u8 = 0x3A as *mut u8;
/// General Purpose IO Register 2.
pub const GPIOR2: *mut u8 = 0x3B as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3C as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x3D as *mut u8;
/// EEPROM Read/Write Access Bytes.
pub const EEAR: *mut u16 = 0x3E as *mut u16;
/// EEPROM Read/Write Access Bytes low byte.
pub const EEARL: *mut u8 = 0x3E as *mut u8;
/// EEPROM Read/Write Access Bytes high byte.
pub const EEARH: *mut u8 = 0x3F as *mut u8;
/// External Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x40 as *mut u8;
/// External Interrupt Mask Register.
pub const EIMSK: *mut u8 = 0x41 as *mut u8;
/// Output Compare SB Register.
pub const OCR0SB: *mut u16 = 0x42 as *mut u16;
/// Output Compare SB Register  low byte.
pub const OCR0SBL: *mut u8 = 0x42 as *mut u8;
/// Output Compare SB Register  high byte.
pub const OCR0SBH: *mut u8 = 0x43 as *mut u8;
/// Output Compare RB Register  low byte.
pub const OCR0RBL: *mut u8 = 0x44 as *mut u8;
/// Output Compare RB Register.
pub const OCR0RB: *mut u16 = 0x44 as *mut u16;
/// Output Compare RB Register  high byte.
pub const OCR0RBH: *mut u8 = 0x45 as *mut u8;
/// Output Compare SB Register  low byte.
pub const OCR2SBL: *mut u8 = 0x46 as *mut u8;
/// Output Compare SB Register.
pub const OCR2SB: *mut u16 = 0x46 as *mut u16;
/// Output Compare SB Register  high byte.
pub const OCR2SBH: *mut u8 = 0x47 as *mut u8;
/// Output Compare RB Register  low byte.
pub const OCR2RBL: *mut u8 = 0x48 as *mut u8;
/// Output Compare RB Register.
pub const OCR2RB: *mut u16 = 0x48 as *mut u16;
/// Output Compare RB Register  high byte.
pub const OCR2RBH: *mut u8 = 0x49 as *mut u8;
/// Output Compare RA Register.
pub const OCR0RA: *mut u16 = 0x4A as *mut u16;
/// Output Compare RA Register  low byte.
pub const OCR0RAL: *mut u8 = 0x4A as *mut u8;
/// Output Compare RA Register  high byte.
pub const OCR0RAH: *mut u8 = 0x4B as *mut u8;
/// ADC Data Register Bytes low byte.
pub const ADCL: *mut u8 = 0x4C as *mut u8;
/// ADC Data Register Bytes.
pub const ADC: *mut u16 = 0x4C as *mut u16;
/// ADC Data Register Bytes high byte.
pub const ADCH: *mut u8 = 0x4D as *mut u8;
/// Output Compare RA Register  low byte.
pub const OCR2RAL: *mut u8 = 0x4E as *mut u8;
/// Output Compare RA Register.
pub const OCR2RA: *mut u16 = 0x4E as *mut u16;
/// Output Compare RA Register  high byte.
pub const OCR2RAH: *mut u8 = 0x4F as *mut u8;
/// Sleep Mode Control Register.
pub const SMCR: *mut u8 = 0x53 as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0x56 as *mut u8;
/// Store Program Memory Control Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// DAC Data Register low byte.
pub const DACL: *mut u8 = 0x58 as *mut u8;
/// DAC Data Register.
pub const DAC: *mut u16 = 0x58 as *mut u16;
/// DAC Data Register high byte.
pub const DACH: *mut u8 = 0x59 as *mut u8;
/// Timer/Counter1 Bytes.
pub const TCNT1: *mut u16 = 0x5A as *mut u16;
/// Timer/Counter1 Bytes low byte.
pub const TCNT1L: *mut u8 = 0x5A as *mut u8;
/// Timer/Counter1 Bytes high byte.
pub const TCNT1H: *mut u8 = 0x5B as *mut u8;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Output Compare SA Register.
pub const OCR0SA: *mut u16 = 0x60 as *mut u16;
/// Output Compare SA Register  low byte.
pub const OCR0SAL: *mut u8 = 0x60 as *mut u8;
/// Output Compare SA Register  high byte.
pub const OCR0SAH: *mut u8 = 0x61 as *mut u8;
/// PSC 0 Input A Control.
pub const PFRC0A: *mut u8 = 0x62 as *mut u8;
/// PSC 0 Input B Control.
pub const PFRC0B: *mut u8 = 0x63 as *mut u8;
/// Output Compare SA Register  low byte.
pub const OCR2SAL: *mut u8 = 0x64 as *mut u8;
/// Output Compare SA Register.
pub const OCR2SA: *mut u16 = 0x64 as *mut u16;
/// Output Compare SA Register  high byte.
pub const OCR2SAH: *mut u8 = 0x65 as *mut u8;
/// PSC 2 Input B Control.
pub const PFRC2A: *mut u8 = 0x66 as *mut u8;
/// PSC 2 Input B Control.
pub const PFRC2B: *mut u8 = 0x67 as *mut u8;
/// PSC 0 Input Capture Register  low byte.
pub const PICR0L: *mut u8 = 0x68 as *mut u8;
/// PSC 0 Input Capture Register.
pub const PICR0: *mut u16 = 0x68 as *mut u16;
/// PSC 0 Input Capture Register  high byte.
pub const PICR0H: *mut u8 = 0x69 as *mut u8;
/// PSC0 Synchro and Output Configuration.
pub const PSOC0: *mut u8 = 0x6A as *mut u8;
/// PSC 2 Input Capture Register low byte.
pub const PICR2L: *mut u8 = 0x6C as *mut u8;
/// PSC 2 Input Capture Register.
pub const PICR2: *mut u16 = 0x6C as *mut u16;
/// PSC 2 Input Capture Register high byte.
pub const PICR2H: *mut u8 = 0x6D as *mut u8;
/// PSC2 Synchro and Output Configuration.
pub const PSOC2: *mut u8 = 0x6E as *mut u8;
/// PSC 2 Output Matrix.
pub const POM2: *mut u8 = 0x6F as *mut u8;
/// PSC 2 Enhanced Configuration Register.
pub const PCNFE2: *mut u8 = 0x70 as *mut u8;
/// Analog Synchronization Delay Register.
pub const PASDLY2: *mut u8 = 0x71 as *mut u8;
/// DAC Control Register.
pub const DACON: *mut u8 = 0x76 as *mut u8;
/// Digital Input Disable Register 0.
pub const DIDR0: *mut u8 = 0x77 as *mut u8;
/// Digital Input Disable Register 1.
pub const DIDR1: *mut u8 = 0x78 as *mut u8;
pub const AMP0CSR: *mut u8 = 0x79 as *mut u8;
pub const AC1ECON: *mut u8 = 0x7A as *mut u8;
pub const AC2ECON: *mut u8 = 0x7B as *mut u8;
pub const AC3ECON: *mut u8 = 0x7C as *mut u8;
/// Analog Comparator 1 Control Register.
pub const AC1CON: *mut u8 = 0x7D as *mut u8;
/// Analog Comparator 2 Control Register.
pub const AC2CON: *mut u8 = 0x7E as *mut u8;
/// Analog Comparator3 Control Register.
pub const AC3CON: *mut u8 = 0x7F as *mut u8;
/// BandGap Resistor Calibration Register.
pub const BGCRR: *mut u8 = 0x80 as *mut u8;
/// BandGap Current Calibration Register.
pub const BGCCR: *mut u8 = 0x81 as *mut u8;
/// Watchdog Timer Control Register.
pub const WDTCSR: *mut u8 = 0x82 as *mut u8;
pub const CLKPR: *mut u8 = 0x83 as *mut u8;
pub const CLKCSR: *mut u8 = 0x84 as *mut u8;
pub const CLKSELR: *mut u8 = 0x85 as *mut u8;
/// Power Reduction Register.
pub const PRR: *mut u8 = 0x86 as *mut u8;
/// PLL Control And Status Register.
pub const PLLCSR: *mut u8 = 0x87 as *mut u8;
/// Oscillator Calibration Value.
pub const OSCCAL: *mut u8 = 0x88 as *mut u8;
/// External Interrupt Control Register A.
pub const EICRA: *mut u8 = 0x89 as *mut u8;
/// Timer/Counter1 Control Register B.
pub const TCCR1B: *mut u8 = 0x8A as *mut u8;
/// Timer/Counter1 Input Capture Register Bytes.
pub const ICR1: *mut u16 = 0x8C as *mut u16;
/// Timer/Counter1 Input Capture Register Bytes low byte.
pub const ICR1L: *mut u8 = 0x8C as *mut u8;
/// Timer/Counter1 Input Capture Register Bytes high byte.
pub const ICR1H: *mut u8 = 0x8D as *mut u8;