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//! The AVR ATtiny840 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | ATtiny840-XBT |  |  | -40°C - 105°C | 1.8V - 5.5V | 16 MHz |
//! | ATtiny840-XNR |  |  | -40°C - 105°C | 1.8V - 5.5V | 16 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTB
//! * PORTC
//! * PORTD
//!
//! ## USART modules
//!
//! * USART1
//!
//! ## EEPROM modules
//!
//! * EEPROM

pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const HIGH: *mut u8 = 0x1 as *mut u8;
pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x23 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x24 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x25 as *mut u8;
/// Port C Input Pins.
pub const PINC: *mut u8 = 0x26 as *mut u8;
/// Port C Data Direction Register.
pub const DDRC: *mut u8 = 0x27 as *mut u8;
/// Port C Data Register.
pub const PORTC: *mut u8 = 0x28 as *mut u8;
/// Port D Input Pins.
pub const PIND: *mut u8 = 0x29 as *mut u8;
/// Port D Data Direction Register.
pub const DDRD: *mut u8 = 0x2A as *mut u8;
/// Port D Data Register.
pub const PORTD: *mut u8 = 0x2B as *mut u8;
/// Analog Comparator Mux register.
pub const ACMUX: *mut u8 = 0x2F as *mut u8;
/// Timer/Counter0 Interrupt Flag register.
pub const TIFR0: *mut u8 = 0x35 as *mut u8;
/// Timer/Counter Interrupt Flag register.
pub const TIFR1: *mut u8 = 0x36 as *mut u8;
/// Timer/Counter2 Interrupt Flag Register.
pub const TIFR2: *mut u8 = 0x37 as *mut u8;
/// Custom Logic Control Register.
pub const CLCR: *mut u8 = 0x38 as *mut u8;
/// Timer/Counter Interrupt Flag register.
pub const TIFR3: *mut u8 = 0x38 as *mut u8;
/// Custom Logic Status Register.
pub const CLSR: *mut u8 = 0x39 as *mut u8;
/// Pin Change Interrupt Flag Register.
pub const PCIFR: *mut u8 = 0x3B as *mut u8;
/// External Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x3C as *mut u8;
/// External Interrupt Mask Register.
pub const EIMSK: *mut u8 = 0x3D as *mut u8;
/// General Purpose I/O Register 0.
pub const GPIOR0: *mut u8 = 0x3E as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3F as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x40 as *mut u8;
/// EEPROM Address Register  Bytes.
pub const EEAR: *mut u16 = 0x41 as *mut u16;
/// EEPROM Address Register  Bytes low byte.
pub const EEARL: *mut u8 = 0x41 as *mut u8;
/// EEPROM Address Register  Bytes high byte.
pub const EEARH: *mut u8 = 0x42 as *mut u8;
/// General Timer/Counter Control Register.
pub const GTCCR: *mut u8 = 0x43 as *mut u8;
/// Timer/Counter  Control Register A.
pub const TCCR0A: *mut u8 = 0x44 as *mut u8;
/// Timer/Counter Control Register B.
pub const TCCR0B: *mut u8 = 0x45 as *mut u8;
/// Timer/Counter0.
pub const TCNT0: *mut u8 = 0x46 as *mut u8;
/// Timer/Counter0 Output Compare Register.
pub const OCR0A: *mut u8 = 0x47 as *mut u8;
/// Timer/Counter0 Output Compare Register.
pub const OCR0B: *mut u8 = 0x48 as *mut u8;
/// General Purpose I/O Register 1.
pub const GPIOR1: *mut u8 = 0x4A as *mut u8;
/// General Purpose I/O Register 2.
pub const GPIOR2: *mut u8 = 0x4B as *mut u8;
/// SPI Control Register.
pub const SPCR: *mut u8 = 0x4C as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0x4D as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0x4E as *mut u8;
/// Analog Comparator Control And Status Register.
pub const ACSR: *mut u8 = 0x50 as *mut u8;
/// Sleep Mode Control Register.
pub const SMCR: *mut u8 = 0x53 as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// Store Program Memory Control and Status Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Watchdog Timer Control Register.
pub const WDTCSR: *mut u8 = 0x60 as *mut u8;
/// Clock Prescale Register.
pub const CLKPR: *mut u8 = 0x61 as *mut u8;
/// Power Reduction Register 0.
pub const PRR0: *mut u8 = 0x64 as *mut u8;
/// Power Reduction Register 1.
pub const PRR1: *mut u8 = 0x65 as *mut u8;
/// Oscillator Calibration Value.
pub const OSCCAL: *mut u8 = 0x66 as *mut u8;
/// Pin Change Interrupt Control Register.
pub const PCICR: *mut u8 = 0x68 as *mut u8;
/// External Interrupt Control Register.
pub const EICRA: *mut u8 = 0x69 as *mut u8;
/// Pin Change Mask Register 0.
pub const PCMSK0: *mut u8 = 0x6B as *mut u8;
/// Pin Change Mask Register 1.
pub const PCMSK1: *mut u8 = 0x6C as *mut u8;
/// Pin Change Mask Register 2.
pub const PCMSK2: *mut u8 = 0x6D as *mut u8;
/// Timer/Counter0 Interrupt Mask Register.
pub const TIMSK0: *mut u8 = 0x6E as *mut u8;
/// Timer/Counter1 Interrupt Mask Register.
pub const TIMSK1: *mut u8 = 0x6F as *mut u8;
/// Timer/Counter2 Interrupt Mask register.
pub const TIMSK2: *mut u8 = 0x70 as *mut u8;
/// Timer/Counter3 Interrupt Mask Register.
pub const TIMSK3: *mut u8 = 0x71 as *mut u8;
/// Digital Input Disable Register 1.
pub const DIDR: *mut u8 = 0x7F as *mut u8;
/// Timer/Counter1 Control Register A.
pub const TCCR1A: *mut u8 = 0x80 as *mut u8;
/// Timer/Counter1 Control Register B.
pub const TCCR1B: *mut u8 = 0x81 as *mut u8;
/// Timer/Counter1 Control Register C.
pub const TCCR1C: *mut u8 = 0x82 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes.
pub const ICR1: *mut u16 = 0x86 as *mut u16;
/// Timer/Counter1 Input Capture Register  Bytes low byte.
pub const ICR1L: *mut u8 = 0x86 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes high byte.
pub const ICR1H: *mut u8 = 0x87 as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes low byte.
pub const OCR1AL: *mut u8 = 0x88 as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes.
pub const OCR1A: *mut u16 = 0x88 as *mut u16;
/// Timer/Counter1 Output Compare Register  Bytes high byte.
pub const OCR1AH: *mut u8 = 0x89 as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes.
pub const OCR1B: *mut u16 = 0x8A as *mut u16;
/// Timer/Counter1 Output Compare Register  Bytes low byte.
pub const OCR1BL: *mut u8 = 0x8A as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes high byte.
pub const OCR1BH: *mut u8 = 0x8B as *mut u8;
/// Timer/Counter3 Control Register A.
pub const TCCR3A: *mut u8 = 0x90 as *mut u8;
/// Timer/Counter3 Control Register B.
pub const TCCR3B: *mut u8 = 0x91 as *mut u8;
/// Timer/Counter3 Control Register C.
pub const TCCR3C: *mut u8 = 0x92 as *mut u8;
/// Timer/Counter3  Bytes low byte.
pub const TCNT1L: *mut u8 = 0x94 as *mut u8;
/// Timer/Counter3  Bytes.
pub const TCNT1: *mut u16 = 0x94 as *mut u16;
/// Timer/Counter3  Bytes high byte.
pub const TCNT1H: *mut u8 = 0x95 as *mut u8;
/// Timer/Counter3 Input Capture Register  Bytes.
pub const ICR3: *mut u16 = 0x96 as *mut u16;
/// Timer/Counter3 Input Capture Register  Bytes low byte.
pub const ICR3L: *mut u8 = 0x96 as *mut u8;
/// Timer/Counter3 Input Capture Register  Bytes high byte.
pub const ICR3H: *mut u8 = 0x97 as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes.
pub const OCR3A: *mut u16 = 0x98 as *mut u16;
/// Timer/Counter3 Output Compare Register  Bytes low byte.
pub const OCR3AL: *mut u8 = 0x98 as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes high byte.
pub const OCR3AH: *mut u8 = 0x99 as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes low byte.
pub const OCR3BL: *mut u8 = 0x9A as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes.
pub const OCR3B: *mut u16 = 0x9A as *mut u16;
/// Timer/Counter3 Output Compare Register  Bytes high byte.
pub const OCR3BH: *mut u8 = 0x9B as *mut u8;
/// Timer/Counter2 Control Register A.
pub const TCCR2A: *mut u8 = 0xB0 as *mut u8;
/// Timer/Counter2 Control Register B.
pub const TCCR2B: *mut u8 = 0xB1 as *mut u8;
/// Timer/Counter2.
pub const TCNT2: *mut u8 = 0xB2 as *mut u8;
/// Timer/Counter2 Output Compare Register A.
pub const OCR2A: *mut u8 = 0xB3 as *mut u8;
/// Timer/Counter2 Output Compare Register B.
pub const OCR2B: *mut u8 = 0xB4 as *mut u8;
/// Asynchronous Status Register.
pub const ASSR: *mut u8 = 0xB6 as *mut u8;
/// USART Control and Status Register A.
pub const UCSR1A: *mut u8 = 0xC8 as *mut u8;
/// USART Control and Status Register B.
pub const UCSR1B: *mut u8 = 0xC9 as *mut u8;
/// USART Control and Status Register C.
pub const UCSR1C: *mut u8 = 0xCA as *mut u8;
/// USART Control and Status Register D.
pub const UCSR1D: *mut u8 = 0xCB as *mut u8;
/// USART Baud Rate Register Bytes.
pub const UBRR1: *mut u16 = 0xCC as *mut u16;
/// USART Baud Rate Register Bytes low byte.
pub const UBRR1L: *mut u8 = 0xCC as *mut u8;
/// USART Baud Rate Register Bytes high byte.
pub const UBRR1H: *mut u8 = 0xCD as *mut u8;
/// USART I/O Data Register.
pub const UDR1: *mut u8 = 0xCE as *mut u8;
pub const DEVID0: *mut u8 = 0xF0 as *mut u8;
pub const DEVID1: *mut u8 = 0xF1 as *mut u8;
pub const DEVID2: *mut u8 = 0xF2 as *mut u8;
pub const DEVID3: *mut u8 = 0xF3 as *mut u8;
pub const DEVID4: *mut u8 = 0xF4 as *mut u8;
pub const DEVID5: *mut u8 = 0xF5 as *mut u8;
pub const DEVID6: *mut u8 = 0xF6 as *mut u8;
pub const DEVID7: *mut u8 = 0xF7 as *mut u8;
pub const DEVID8: *mut u8 = 0xF8 as *mut u8;