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//! The AVR ATmega128 microcontroller //! //! # Variants //! | | Pinout | Package | Operating temperature | Operating voltage | Max speed | //! |--------|--------|---------|-----------------------|-------------------|-----------| //! | ATmega128L-8AU | TQFPQFN64 | TQFP64 | -40°C - 85°C | 2.7V - 5.5V | 8 MHz | //! | ATmega128L-8MU | TQFPQFN64 | QFN64 | -40°C - 85°C | 2.7V - 5.5V | 8 MHz | //! | ATmega128-16AU | TQFPQFN64 | TQFP64 | -40°C - 85°C | 4.5V - 5.5V | 16 MHz | //! | ATmega128-16MU | TQFPQFN64 | QFN64 | -40°C - 85°C | 4.5V - 5.5V | 16 MHz | //! | ATmega128L-8AN | TQFPQFN64 | TQFP64 | -40°C - 105°C | 3V - 5.5V | 8 MHz | //! | ATmega128L-8MN | TQFPQFN64 | QFN64 | -40°C - 105°C | 3V - 5.5V | 8 MHz | //! | ATmega128-16AN | TQFPQFN64 | TQFP64 | -40°C - 105°C | 4.5V - 5.5V | 16 MHz | //! | ATmega128-16MN | TQFPQFN64 | QFN64 | -40°C - 105°C | 4.5V - 5.5V | 16 MHz | //! //! # Registers by module (not exhaustive) //! //! ## PORT modules //! //! * PORTA //! * PA0 (PA0) //! * PA1 (PA1) //! * PA2 (PA2) //! * PA3 (PA3) //! * PA4 (PA4) //! * PA5 (PA5) //! * PA6 (PA6) //! * PA7 (PA7) //! * PORTB //! * PB0 (PB0) //! * PB1 (PB1) //! * PB2 (PB2) //! * PB3 (PB3) //! * PB4 (PB4) //! * PB5 (PB5) //! * PB6 (PB6) //! * PB7 (PB7) //! * PORTC //! * PC0 (PC0) //! * PC1 (PC1) //! * PC2 (PC2) //! * PC3 (PC3) //! * PC4 (PC4) //! * PC5 (PC5) //! * PC6 (PC6) //! * PC7 (PC7) //! * PORTD //! * PD0 (PD0) //! * PD1 (PD1) //! * PD2 (PD2) //! * PD3 (PD3) //! * PD4 (PD4) //! * PD5 (PD5) //! * PD6 (PD6) //! * PD7 (PD7) //! * PORTE //! * PE0 (PE0) //! * PE1 (PE1) //! * PE2 (PE2) //! * PE3 (PE3) //! * PE4 (PE4) //! * PE5 (PE5) //! * PE6 (PE6) //! * PE7 (PE7) //! * PORTF //! * PF0 (PF0) //! * PF1 (PF1) //! * PF2 (PF2) //! * PF3 (PF3) //! * PF4 (PF4) //! * PF5 (PF5) //! * PF6 (PF6) //! * PF7 (PF7) //! * PORTG //! * PG0 (PG0) //! * PG1 (PG1) //! * PG2 (PG2) //! * PG3 (PG3) //! * PG4 (PG4) //! //! ## USART modules //! //! * USART0 //! * PE2 (PE2) //! * PE1 (PE1) //! * PE0 (PE0) //! * USART1 //! * PD5 (PD5) //! * PD3 (PD3) //! * PD2 (PD2) //! //! ## JTAG modules //! //! * JTAG //! * PF7 (PF7) //! * PF6 (PF6) //! * PF5 (PF5) //! * PF4 (PF4) //! //! ## EEPROM modules //! //! * EEPROM //! //! ## ADC modules //! //! * ADC //! * PF7 (PF7) //! * PF6 (PF6) //! * PF5 (PF5) //! * PF4 (PF4) //! * PF3 (PF3) //! * PF2 (PF2) //! * PF1 (PF1) //! * PF0 (PF0) pub const LOW: *mut u8 = 0x0 as *mut u8; pub const LOCKBIT: *mut u8 = 0x0 as *mut u8; pub const HIGH: *mut u8 = 0x1 as *mut u8; pub const EXTENDED: *mut u8 = 0x2 as *mut u8; /// Input Pins, Port F. pub const PINF: *mut u8 = 0x20 as *mut u8; /// Input Pins, Port E. pub const PINE: *mut u8 = 0x21 as *mut u8; /// Data Direction Register, Port E. pub const DDRE: *mut u8 = 0x22 as *mut u8; /// Data Register, Port E. pub const PORTE: *mut u8 = 0x23 as *mut u8; /// ADC Data Register Bytes. pub const ADC: *mut u16 = 0x24 as *mut u16; /// ADC Data Register Bytes low byte. pub const ADCL: *mut u8 = 0x24 as *mut u8; /// ADC Data Register Bytes high byte. pub const ADCH: *mut u8 = 0x25 as *mut u8; /// The ADC Control and Status register. pub const ADCSRA: *mut u8 = 0x26 as *mut u8; /// The ADC multiplexer Selection Register. pub const ADMUX: *mut u8 = 0x27 as *mut u8; /// Analog Comparator Control And Status Register. pub const ACSR: *mut u8 = 0x28 as *mut u8; /// USART Baud Rate Register Low Byte. pub const UBRR0L: *mut u8 = 0x29 as *mut u8; /// USART Control and Status Register B. pub const UCSR0B: *mut u8 = 0x2A as *mut u8; /// USART Control and Status Register A. pub const UCSR0A: *mut u8 = 0x2B as *mut u8; /// USART I/O Data Register. pub const UDR0: *mut u8 = 0x2C as *mut u8; /// SPI Control Register. pub const SPCR: *mut u8 = 0x2D as *mut u8; /// SPI Status Register. pub const SPSR: *mut u8 = 0x2E as *mut u8; /// SPI Data Register. pub const SPDR: *mut u8 = 0x2F as *mut u8; /// Port D Input Pins. pub const PIND: *mut u8 = 0x30 as *mut u8; /// Port D Data Direction Register. pub const DDRD: *mut u8 = 0x31 as *mut u8; /// Port D Data Register. pub const PORTD: *mut u8 = 0x32 as *mut u8; /// Port C Input Pins. pub const PINC: *mut u8 = 0x33 as *mut u8; /// Port C Data Direction Register. pub const DDRC: *mut u8 = 0x34 as *mut u8; /// Port C Data Register. pub const PORTC: *mut u8 = 0x35 as *mut u8; /// Port B Input Pins. pub const PINB: *mut u8 = 0x36 as *mut u8; /// Port B Data Direction Register. pub const DDRB: *mut u8 = 0x37 as *mut u8; /// Port B Data Register. pub const PORTB: *mut u8 = 0x38 as *mut u8; /// Port A Input Pins. pub const PINA: *mut u8 = 0x39 as *mut u8; /// Port A Data Direction Register. pub const DDRA: *mut u8 = 0x3A as *mut u8; /// Port A Data Register. pub const PORTA: *mut u8 = 0x3B as *mut u8; /// EEPROM Control Register. pub const EECR: *mut u8 = 0x3C as *mut u8; /// EEPROM Data Register. pub const EEDR: *mut u8 = 0x3D as *mut u8; /// EEPROM Read/Write Access Bytes. pub const EEAR: *mut u16 = 0x3E as *mut u16; /// EEPROM Read/Write Access Bytes low byte. pub const EEARL: *mut u8 = 0x3E as *mut u8; /// EEPROM Read/Write Access Bytes high byte. pub const EEARH: *mut u8 = 0x3F as *mut u8; /// Special Function IO Register. pub const SFIOR: *mut u8 = 0x40 as *mut u8; /// Watchdog Timer Control Register. pub const WDTCR: *mut u8 = 0x41 as *mut u8; /// On-Chip Debug Related Register in I/O Memory. pub const OCDR: *mut u8 = 0x42 as *mut u8; /// Output Compare Register. pub const OCR2: *mut u8 = 0x43 as *mut u8; /// Timer/Counter Register. pub const TCNT2: *mut u8 = 0x44 as *mut u8; /// Timer/Counter Control Register. pub const TCCR2: *mut u8 = 0x45 as *mut u8; /// Timer/Counter1 Input Capture Register Bytes low byte. pub const ICR1L: *mut u8 = 0x46 as *mut u8; /// Timer/Counter1 Input Capture Register Bytes. pub const ICR1: *mut u16 = 0x46 as *mut u16; /// Timer/Counter1 Input Capture Register Bytes high byte. pub const ICR1H: *mut u8 = 0x47 as *mut u8; /// Timer/Counter1 Output Compare Register Bytes. pub const OCR1B: *mut u16 = 0x48 as *mut u16; /// Timer/Counter1 Output Compare Register Bytes low byte. pub const OCR1BL: *mut u8 = 0x48 as *mut u8; /// Timer/Counter1 Output Compare Register Bytes high byte. pub const OCR1BH: *mut u8 = 0x49 as *mut u8; /// Timer/Counter1 Output Compare Register Bytes low byte. pub const OCR1AL: *mut u8 = 0x4A as *mut u8; /// Timer/Counter1 Output Compare Register Bytes. pub const OCR1A: *mut u16 = 0x4A as *mut u16; /// Timer/Counter1 Output Compare Register Bytes high byte. pub const OCR1AH: *mut u8 = 0x4B as *mut u8; /// Timer/Counter1 Bytes. pub const TCNT1: *mut u16 = 0x4C as *mut u16; /// Timer/Counter1 Bytes low byte. pub const TCNT1L: *mut u8 = 0x4C as *mut u8; /// Timer/Counter1 Bytes high byte. pub const TCNT1H: *mut u8 = 0x4D as *mut u8; /// Timer/Counter1 Control Register B. pub const TCCR1B: *mut u8 = 0x4E as *mut u8; /// Timer/Counter1 Control Register A. pub const TCCR1A: *mut u8 = 0x4F as *mut u8; /// Asynchronus Status Register. pub const ASSR: *mut u8 = 0x50 as *mut u8; /// Output Compare Register. pub const OCR0: *mut u8 = 0x51 as *mut u8; /// Timer/Counter Register. pub const TCNT0: *mut u8 = 0x52 as *mut u8; /// Timer/Counter Control Register. pub const TCCR0: *mut u8 = 0x53 as *mut u8; /// MCU Control And Status Register. pub const MCUCSR: *mut u8 = 0x54 as *mut u8; /// MCU Control Register. pub const MCUCR: *mut u8 = 0x55 as *mut u8; /// Timer/Counter Interrupt Flag Register. pub const TIFR: *mut u8 = 0x56 as *mut u8; pub const TIMSK: *mut u8 = 0x57 as *mut u8; /// External Interrupt Flag Register. pub const EIFR: *mut u8 = 0x58 as *mut u8; /// External Interrupt Mask Register. pub const EIMSK: *mut u8 = 0x59 as *mut u8; /// External Interrupt Control Register B. pub const EICRB: *mut u8 = 0x5A as *mut u8; /// RAM Page Z Select Register. pub const RAMPZ: *mut u8 = 0x5B as *mut u8; /// XTAL Divide Control Register. pub const XDIV: *mut u8 = 0x5C as *mut u8; /// Stack Pointer low byte. pub const SPL: *mut u8 = 0x5D as *mut u8; /// Stack Pointer. pub const SP: *mut u16 = 0x5D as *mut u16; /// Stack Pointer high byte. pub const SPH: *mut u8 = 0x5E as *mut u8; /// Status Register. pub const SREG: *mut u8 = 0x5F as *mut u8; /// Data Direction Register, Port F. pub const DDRF: *mut u8 = 0x61 as *mut u8; /// Data Register, Port F. pub const PORTF: *mut u8 = 0x62 as *mut u8; /// Input Pins, Port G. pub const PING: *mut u8 = 0x63 as *mut u8; /// Data Direction Register, Port G. pub const DDRG: *mut u8 = 0x64 as *mut u8; /// Data Register, Port G. pub const PORTG: *mut u8 = 0x65 as *mut u8; /// Store Program Memory Control Register. pub const SPMCSR: *mut u8 = 0x68 as *mut u8; /// External Interrupt Control Register A. pub const EICRA: *mut u8 = 0x6A as *mut u8; /// External Memory Control Register B. pub const XMCRB: *mut u8 = 0x6C as *mut u8; /// External Memory Control Register A. pub const XMCRA: *mut u8 = 0x6D as *mut u8; /// Oscillator Calibration Value. pub const OSCCAL: *mut u8 = 0x6F as *mut u8; /// TWI Bit Rate register. pub const TWBR: *mut u8 = 0x70 as *mut u8; /// TWI Status Register. pub const TWSR: *mut u8 = 0x71 as *mut u8; /// TWI (Slave) Address register. pub const TWAR: *mut u8 = 0x72 as *mut u8; /// TWI Data register. pub const TWDR: *mut u8 = 0x73 as *mut u8; /// TWI Control Register. pub const TWCR: *mut u8 = 0x74 as *mut u8; /// Timer/Counter1 Output Compare Register Bytes low byte. pub const OCR1CL: *mut u8 = 0x78 as *mut u8; /// Timer/Counter1 Output Compare Register Bytes. pub const OCR1C: *mut u16 = 0x78 as *mut u16; /// Timer/Counter1 Output Compare Register Bytes high byte. pub const OCR1CH: *mut u8 = 0x79 as *mut u8; /// Timer/Counter1 Control Register C. pub const TCCR1C: *mut u8 = 0x7A as *mut u8; /// Extended Timer/Counter Interrupt Flag register. pub const ETIFR: *mut u8 = 0x7C as *mut u8; /// Extended Timer/Counter Interrupt Mask Register. pub const ETIMSK: *mut u8 = 0x7D as *mut u8; /// Timer/Counter3 Input Capture Register Bytes low byte. pub const ICR3L: *mut u8 = 0x80 as *mut u8; /// Timer/Counter3 Input Capture Register Bytes. pub const ICR3: *mut u16 = 0x80 as *mut u16; /// Timer/Counter3 Input Capture Register Bytes high byte. pub const ICR3H: *mut u8 = 0x81 as *mut u8; /// Timer/Counter3 Output compare Register C Bytes low byte. pub const OCR3CL: *mut u8 = 0x82 as *mut u8; /// Timer/Counter3 Output compare Register C Bytes. pub const OCR3C: *mut u16 = 0x82 as *mut u16; /// Timer/Counter3 Output compare Register C Bytes high byte. pub const OCR3CH: *mut u8 = 0x83 as *mut u8; /// Timer/Counter3 Output Compare Register B Bytes. pub const OCR3B: *mut u16 = 0x84 as *mut u16; /// Timer/Counter3 Output Compare Register B Bytes low byte. pub const OCR3BL: *mut u8 = 0x84 as *mut u8; /// Timer/Counter3 Output Compare Register B Bytes high byte. pub const OCR3BH: *mut u8 = 0x85 as *mut u8; /// Timer/Counter3 Output Compare Register A Bytes. pub const OCR3A: *mut u16 = 0x86 as *mut u16; /// Timer/Counter3 Output Compare Register A Bytes low byte. pub const OCR3AL: *mut u8 = 0x86 as *mut u8; /// Timer/Counter3 Output Compare Register A Bytes high byte. pub const OCR3AH: *mut u8 = 0x87 as *mut u8; /// Timer/Counter3 Bytes. pub const TCNT3: *mut u16 = 0x88 as *mut u16; /// Timer/Counter3 Bytes low byte. pub const TCNT3L: *mut u8 = 0x88 as *mut u8; /// Timer/Counter3 Bytes high byte. pub const TCNT3H: *mut u8 = 0x89 as *mut u8; /// Timer/Counter3 Control Register B. pub const TCCR3B: *mut u8 = 0x8A as *mut u8; /// Timer/Counter3 Control Register A. pub const TCCR3A: *mut u8 = 0x8B as *mut u8; /// Timer/Counter3 Control Register C. pub const TCCR3C: *mut u8 = 0x8C as *mut u8; /// USART Baud Rate Register Hight Byte. pub const UBRR0H: *mut u8 = 0x90 as *mut u8; /// USART Control and Status Register C. pub const UCSR0C: *mut u8 = 0x95 as *mut u8; /// USART Baud Rate Register Hight Byte. pub const UBRR1H: *mut u8 = 0x98 as *mut u8; /// USART Baud Rate Register Low Byte. pub const UBRR1L: *mut u8 = 0x99 as *mut u8; /// USART Control and Status Register B. pub const UCSR1B: *mut u8 = 0x9A as *mut u8; /// USART Control and Status Register A. pub const UCSR1A: *mut u8 = 0x9B as *mut u8; /// USART I/O Data Register. pub const UDR1: *mut u8 = 0x9C as *mut u8; /// USART Control and Status Register C. pub const UCSR1C: *mut u8 = 0x9D as *mut u8;