//! The AVR AT90CAN32 microcontroller
//!
//! # Variants
//! |        | Pinout | Package | Operating temperature | Operating voltage | Max speed |
//! |--------|--------|---------|-----------------------|-------------------|-----------|
//! | AT90CAN32-16AI | TQFP64 | TQFP64 | -40°C - 85°C | 2.7V - 5.5V | 16 MHz |
//! | AT90CAN32-16MI | QFN64 | QFN64 | -40°C - 85°C | 2.7V - 5.5V | 16 MHz |
//! | AT90CAN32-16AU | TQFP64 | TQFP64 | -40°C - 85°C | 2.7V - 5.5V | 16 MHz |
//! | AT90CAN32-16MU | QFN64 | QFN64 | -40°C - 85°C | 2.7V - 5.5V | 16 MHz |
//!
//! # Registers by module (not exhaustive)
//!
//! ## PORT modules
//!
//! * PORTA
//!     * PA0 (PA0)
//!     * PA1 (PA1)
//!     * PA2 (PA2)
//!     * PA3 (PA3)
//!     * PA4 (PA4)
//!     * PA5 (PA5)
//!     * PA6 (PA6)
//!     * PA7 (PA7)
//! * PORTB
//!     * PB0 (PB0)
//!     * PB1 (PB1)
//!     * PB2 (PB2)
//!     * PB3 (PB3)
//!     * PB4 (PB4)
//!     * PB5 (PB5)
//!     * PB6 (PB6)
//!     * PB7 (PB7)
//! * PORTC
//!     * PC0 (PC0)
//!     * PC1 (PC1)
//!     * PC2 (PC2)
//!     * PC3 (PC3)
//!     * PC4 (PC4)
//!     * PC5 (PC5)
//!     * PC6 (PC6)
//!     * PC7 (PC7)
//! * PORTD
//!     * PD0 (PD0)
//!     * PD1 (PD1)
//!     * PD2 (PD2)
//!     * PD3 (PD3)
//!     * PD4 (PD4)
//!     * PD5 (PD5)
//!     * PD6 (PD6)
//!     * PD7 (PD7)
//! * PORTE
//!     * PE0 (PE0)
//!     * PE1 (PE1)
//!     * PE2 (PE2)
//!     * PE3 (PE3)
//!     * PE4 (PE4)
//!     * PE5 (PE5)
//!     * PE6 (PE6)
//!     * PE7 (PE7)
//! * PORTF
//!     * PF0 (PF0)
//!     * PF1 (PF1)
//!     * PF2 (PF2)
//!     * PF3 (PF3)
//!     * PF4 (PF4)
//!     * PF5 (PF5)
//!     * PF6 (PF6)
//!     * PF7 (PF7)
//! * PORTG
//!     * PG0 (PG0)
//!     * PG1 (PG1)
//!     * PG2 (PG2)
//!     * PG3 (PG3)
//!     * PG4 (PG4)
//!     * PG5 (PG5)
//!     * PG6 (PG6)
//!     * PG7 (PG7)
//!
//! ## JTAG modules
//!
//! * JTAG
//!     * PF4 (PF4)
//!     * PF5 (PF5)
//!     * PF6 (PF6)
//!     * PF7 (PF7)
//!
//! ## USART modules
//!
//! * USART0
//!     * PE1 (PE1)
//!     * PE0 (PE0)
//!     * PE2 (PE2)
//! * USART1
//!     * PD3 (PD3)
//!     * PD2 (PD2)
//!     * PD5 (PD5)
//!
//! ## EEPROM modules
//!
//! * EEPROM
//!
//! ## ADC modules
//!
//! * ADC
//!     * PA0 (PA0)
//!     * PA1 (PA1)
//!     * PA2 (PA2)
//!     * PA3 (PA3)
//!     * PA4 (PA4)
//!     * PA5 (PA5)
//!     * PA6 (PA6)
//!     * PA7 (PA7)

pub const LOW: *mut u8 = 0x0 as *mut u8;
pub const LOCKBIT: *mut u8 = 0x0 as *mut u8;
pub const HIGH: *mut u8 = 0x1 as *mut u8;
pub const EXTENDED: *mut u8 = 0x2 as *mut u8;
/// Port A Input Pins.
pub const PINA: *mut u8 = 0x20 as *mut u8;
/// Port A Data Direction Register.
pub const DDRA: *mut u8 = 0x21 as *mut u8;
/// Port A Data Register.
pub const PORTA: *mut u8 = 0x22 as *mut u8;
/// Port B Input Pins.
pub const PINB: *mut u8 = 0x23 as *mut u8;
/// Port B Data Direction Register.
pub const DDRB: *mut u8 = 0x24 as *mut u8;
/// Port B Data Register.
pub const PORTB: *mut u8 = 0x25 as *mut u8;
/// Port C Input Pins.
pub const PINC: *mut u8 = 0x26 as *mut u8;
/// Port C Data Direction Register.
pub const DDRC: *mut u8 = 0x27 as *mut u8;
/// Port C Data Register.
pub const PORTC: *mut u8 = 0x28 as *mut u8;
/// Port D Input Pins.
pub const PIND: *mut u8 = 0x29 as *mut u8;
/// Port D Data Direction Register.
pub const DDRD: *mut u8 = 0x2A as *mut u8;
/// Port D Data Register.
pub const PORTD: *mut u8 = 0x2B as *mut u8;
/// Input Pins, Port E.
pub const PINE: *mut u8 = 0x2C as *mut u8;
/// Data Direction Register, Port E.
pub const DDRE: *mut u8 = 0x2D as *mut u8;
/// Data Register, Port E.
pub const PORTE: *mut u8 = 0x2E as *mut u8;
/// Input Pins, Port F.
pub const PINF: *mut u8 = 0x2F as *mut u8;
/// Data Direction Register, Port F.
pub const DDRF: *mut u8 = 0x30 as *mut u8;
/// Data Register, Port F.
pub const PORTF: *mut u8 = 0x31 as *mut u8;
/// Input Pins, Port G.
pub const PING: *mut u8 = 0x32 as *mut u8;
/// Data Direction Register, Port G.
pub const DDRG: *mut u8 = 0x33 as *mut u8;
/// Data Register, Port G.
pub const PORTG: *mut u8 = 0x34 as *mut u8;
/// Timer/Counter0 Interrupt Flag register.
pub const TIFR0: *mut u8 = 0x35 as *mut u8;
/// Timer/Counter Interrupt Flag register.
pub const TIFR1: *mut u8 = 0x36 as *mut u8;
/// Timer/Counter Interrupt Flag Register.
pub const TIFR2: *mut u8 = 0x37 as *mut u8;
/// Timer/Counter Interrupt Flag register.
pub const TIFR3: *mut u8 = 0x38 as *mut u8;
/// External Interrupt Flag Register.
pub const EIFR: *mut u8 = 0x3C as *mut u8;
/// External Interrupt Mask Register.
pub const EIMSK: *mut u8 = 0x3D as *mut u8;
/// General Purpose IO Register 0.
pub const GPIOR0: *mut u8 = 0x3E as *mut u8;
/// EEPROM Control Register.
pub const EECR: *mut u8 = 0x3F as *mut u8;
/// EEPROM Data Register.
pub const EEDR: *mut u8 = 0x40 as *mut u8;
/// EEPROM Read/Write Access Bytes low byte.
pub const EEARL: *mut u8 = 0x41 as *mut u8;
/// EEPROM Read/Write Access Bytes.
pub const EEAR: *mut u16 = 0x41 as *mut u16;
/// EEPROM Read/Write Access Bytes high byte.
pub const EEARH: *mut u8 = 0x42 as *mut u8;
/// General Timer/Counter Control Register.
pub const GTCCR: *mut u8 = 0x43 as *mut u8;
/// Timer/Counter0 Control Register.
pub const TCCR0A: *mut u8 = 0x44 as *mut u8;
/// Timer/Counter0.
pub const TCNT0: *mut u8 = 0x46 as *mut u8;
/// Timer/Counter0 Output Compare Register.
pub const OCR0A: *mut u8 = 0x47 as *mut u8;
/// General Purpose IO Register 1.
pub const GPIOR1: *mut u8 = 0x4A as *mut u8;
/// General Purpose IO Register 2.
pub const GPIOR2: *mut u8 = 0x4B as *mut u8;
/// SPI Control Register.
pub const SPCR: *mut u8 = 0x4C as *mut u8;
/// SPI Status Register.
pub const SPSR: *mut u8 = 0x4D as *mut u8;
/// SPI Data Register.
pub const SPDR: *mut u8 = 0x4E as *mut u8;
/// Analog Comparator Control And Status Register.
pub const ACSR: *mut u8 = 0x50 as *mut u8;
/// On-Chip Debug Related Register in I/O Memory.
pub const OCDR: *mut u8 = 0x51 as *mut u8;
/// Sleep Mode Control Register.
pub const SMCR: *mut u8 = 0x53 as *mut u8;
/// MCU Status Register.
pub const MCUSR: *mut u8 = 0x54 as *mut u8;
/// MCU Control Register.
pub const MCUCR: *mut u8 = 0x55 as *mut u8;
/// Store Program Memory Control Register.
pub const SPMCSR: *mut u8 = 0x57 as *mut u8;
/// RAM Page Z Select Register - Not used.
pub const RAMPZ: *mut u8 = 0x5B as *mut u8;
/// Stack Pointer  low byte.
pub const SPL: *mut u8 = 0x5D as *mut u8;
/// Stack Pointer.
pub const SP: *mut u16 = 0x5D as *mut u16;
/// Stack Pointer  high byte.
pub const SPH: *mut u8 = 0x5E as *mut u8;
/// Status Register.
pub const SREG: *mut u8 = 0x5F as *mut u8;
/// Watchdog Timer Control Register.
pub const WDTCR: *mut u8 = 0x60 as *mut u8;
/// Clock Prescale Register.
pub const CLKPR: *mut u8 = 0x61 as *mut u8;
/// Oscillator Calibration Value.
pub const OSCCAL: *mut u8 = 0x66 as *mut u8;
/// External Interrupt Control Register A.
pub const EICRA: *mut u8 = 0x69 as *mut u8;
/// External Interrupt Control Register B.
pub const EICRB: *mut u8 = 0x6A as *mut u8;
/// Timer/Counter0 Interrupt Mask Register.
pub const TIMSK0: *mut u8 = 0x6E as *mut u8;
/// Timer/Counter Interrupt Mask Register.
pub const TIMSK1: *mut u8 = 0x6F as *mut u8;
/// Timer/Counter Interrupt Mask register.
pub const TIMSK2: *mut u8 = 0x70 as *mut u8;
/// Timer/Counter Interrupt Mask Register.
pub const TIMSK3: *mut u8 = 0x71 as *mut u8;
/// External Memory Control Register A.
pub const XMCRA: *mut u8 = 0x74 as *mut u8;
/// External Memory Control Register B.
pub const XMCRB: *mut u8 = 0x75 as *mut u8;
/// ADC Data Register  Bytes.
pub const ADC: *mut u16 = 0x78 as *mut u16;
/// ADC Data Register  Bytes low byte.
pub const ADCL: *mut u8 = 0x78 as *mut u8;
/// ADC Data Register  Bytes high byte.
pub const ADCH: *mut u8 = 0x79 as *mut u8;
/// The ADC Control and Status register.
pub const ADCSRA: *mut u8 = 0x7A as *mut u8;
/// ADC Control and Status Register B.
pub const ADCSRB: *mut u8 = 0x7B as *mut u8;
/// The ADC multiplexer Selection Register.
pub const ADMUX: *mut u8 = 0x7C as *mut u8;
/// Digital Input Disable Register 1.
pub const DIDR0: *mut u8 = 0x7E as *mut u8;
pub const DIDR1: *mut u8 = 0x7F as *mut u8;
/// Timer/Counter1 Control Register A.
pub const TCCR1A: *mut u8 = 0x80 as *mut u8;
/// Timer/Counter1 Control Register B.
pub const TCCR1B: *mut u8 = 0x81 as *mut u8;
/// Timer/Counter 1 Control Register C.
pub const TCCR1C: *mut u8 = 0x82 as *mut u8;
/// Timer/Counter1  Bytes.
pub const TCNT1: *mut u16 = 0x84 as *mut u16;
/// Timer/Counter1  Bytes low byte.
pub const TCNT1L: *mut u8 = 0x84 as *mut u8;
/// Timer/Counter1  Bytes high byte.
pub const TCNT1H: *mut u8 = 0x85 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes low byte.
pub const ICR1L: *mut u8 = 0x86 as *mut u8;
/// Timer/Counter1 Input Capture Register  Bytes.
pub const ICR1: *mut u16 = 0x86 as *mut u16;
/// Timer/Counter1 Input Capture Register  Bytes high byte.
pub const ICR1H: *mut u8 = 0x87 as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes low byte.
pub const OCR1AL: *mut u8 = 0x88 as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes.
pub const OCR1A: *mut u16 = 0x88 as *mut u16;
/// Timer/Counter1 Output Compare Register  Bytes high byte.
pub const OCR1AH: *mut u8 = 0x89 as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes low byte.
pub const OCR1BL: *mut u8 = 0x8A as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes.
pub const OCR1B: *mut u16 = 0x8A as *mut u16;
/// Timer/Counter1 Output Compare Register  Bytes high byte.
pub const OCR1BH: *mut u8 = 0x8B as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes low byte.
pub const OCR1CL: *mut u8 = 0x8C as *mut u8;
/// Timer/Counter1 Output Compare Register  Bytes.
pub const OCR1C: *mut u16 = 0x8C as *mut u16;
/// Timer/Counter1 Output Compare Register  Bytes high byte.
pub const OCR1CH: *mut u8 = 0x8D as *mut u8;
/// Timer/Counter3 Control Register A.
pub const TCCR3A: *mut u8 = 0x90 as *mut u8;
/// Timer/Counter3 Control Register B.
pub const TCCR3B: *mut u8 = 0x91 as *mut u8;
/// Timer/Counter 3 Control Register C.
pub const TCCR3C: *mut u8 = 0x92 as *mut u8;
/// Timer/Counter3  Bytes low byte.
pub const TCNT3L: *mut u8 = 0x94 as *mut u8;
/// Timer/Counter3  Bytes.
pub const TCNT3: *mut u16 = 0x94 as *mut u16;
/// Timer/Counter3  Bytes high byte.
pub const TCNT3H: *mut u8 = 0x95 as *mut u8;
/// Timer/Counter3 Input Capture Register  Bytes low byte.
pub const ICR3L: *mut u8 = 0x96 as *mut u8;
/// Timer/Counter3 Input Capture Register  Bytes.
pub const ICR3: *mut u16 = 0x96 as *mut u16;
/// Timer/Counter3 Input Capture Register  Bytes high byte.
pub const ICR3H: *mut u8 = 0x97 as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes low byte.
pub const OCR3AL: *mut u8 = 0x98 as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes.
pub const OCR3A: *mut u16 = 0x98 as *mut u16;
/// Timer/Counter3 Output Compare Register  Bytes high byte.
pub const OCR3AH: *mut u8 = 0x99 as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes low byte.
pub const OCR3BL: *mut u8 = 0x9A as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes.
pub const OCR3B: *mut u16 = 0x9A as *mut u16;
/// Timer/Counter3 Output Compare Register  Bytes high byte.
pub const OCR3BH: *mut u8 = 0x9B as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes.
pub const OCR3C: *mut u16 = 0x9C as *mut u16;
/// Timer/Counter3 Output Compare Register  Bytes low byte.
pub const OCR3CL: *mut u8 = 0x9C as *mut u8;
/// Timer/Counter3 Output Compare Register  Bytes high byte.
pub const OCR3CH: *mut u8 = 0x9D as *mut u8;
/// Timer/Counter2 Control Register.
pub const TCCR2A: *mut u8 = 0xB0 as *mut u8;
/// Timer/Counter2.
pub const TCNT2: *mut u8 = 0xB2 as *mut u8;
/// Timer/Counter2 Output Compare Register.
pub const OCR2A: *mut u8 = 0xB3 as *mut u8;
/// Asynchronous Status Register.
pub const ASSR: *mut u8 = 0xB6 as *mut u8;
/// TWI Bit Rate register.
pub const TWBR: *mut u8 = 0xB8 as *mut u8;
/// TWI Status Register.
pub const TWSR: *mut u8 = 0xB9 as *mut u8;
/// TWI (Slave) Address register.
pub const TWAR: *mut u8 = 0xBA as *mut u8;
/// TWI Data register.
pub const TWDR: *mut u8 = 0xBB as *mut u8;
/// TWI Control Register.
pub const TWCR: *mut u8 = 0xBC as *mut u8;
/// USART Control and Status Register A.
pub const UCSR0A: *mut u8 = 0xC0 as *mut u8;
/// USART Control and Status Register B.
pub const UCSR0B: *mut u8 = 0xC1 as *mut u8;
/// USART Control and Status Register C.
pub const UCSR0C: *mut u8 = 0xC2 as *mut u8;
/// USART Baud Rate Register t Bytes.
pub const UBRR0: *mut u16 = 0xC4 as *mut u16;
/// USART Baud Rate Register t Bytes low byte.
pub const UBRR0L: *mut u8 = 0xC4 as *mut u8;
/// USART Baud Rate Register t Bytes high byte.
pub const UBRR0H: *mut u8 = 0xC5 as *mut u8;
/// USART I/O Data Register.
pub const UDR0: *mut u8 = 0xC6 as *mut u8;
/// USART Control and Status Register A.
pub const UCSR1A: *mut u8 = 0xC8 as *mut u8;
/// USART Control and Status Register B.
pub const UCSR1B: *mut u8 = 0xC9 as *mut u8;
/// USART Control and Status Register C.
pub const UCSR1C: *mut u8 = 0xCA as *mut u8;
/// USART Baud Rate Register t Bytes low byte.
pub const UBRR1L: *mut u8 = 0xCC as *mut u8;
/// USART Baud Rate Register t Bytes.
pub const UBRR1: *mut u16 = 0xCC as *mut u16;
/// USART Baud Rate Register t Bytes high byte.
pub const UBRR1H: *mut u8 = 0xCD as *mut u8;
/// USART I/O Data Register.
pub const UDR1: *mut u8 = 0xCE as *mut u8;
/// CAN General Control Register.
pub const CANGCON: *mut u8 = 0xD8 as *mut u8;
/// CAN General Status Register.
pub const CANGSTA: *mut u8 = 0xD9 as *mut u8;
/// CAN General Interrupt Register.
pub const CANGIT: *mut u8 = 0xDA as *mut u8;
/// CAN General Interrupt Enable Register.
pub const CANGIE: *mut u8 = 0xDB as *mut u8;
/// Enable MOb Register.
pub const CANEN2: *mut u8 = 0xDC as *mut u8;
/// Enable MOb Register.
pub const CANEN1: *mut u8 = 0xDD as *mut u8;
/// Enable Interrupt MOb Register.
pub const CANIE2: *mut u8 = 0xDE as *mut u8;
/// Enable Interrupt MOb Register.
pub const CANIE1: *mut u8 = 0xDF as *mut u8;
/// CAN Status Interrupt MOb Register.
pub const CANSIT2: *mut u8 = 0xE0 as *mut u8;
/// CAN Status Interrupt MOb Register.
pub const CANSIT1: *mut u8 = 0xE1 as *mut u8;
/// Bit Timing Register 1.
pub const CANBT1: *mut u8 = 0xE2 as *mut u8;
/// Bit Timing Register 2.
pub const CANBT2: *mut u8 = 0xE3 as *mut u8;
/// Bit Timing Register 3.
pub const CANBT3: *mut u8 = 0xE4 as *mut u8;
/// Timer Control Register.
pub const CANTCON: *mut u8 = 0xE5 as *mut u8;
/// Timer Register.
pub const CANTIM: *mut u16 = 0xE6 as *mut u16;
/// Timer Register low byte.
pub const CANTIML: *mut u8 = 0xE6 as *mut u8;
/// Timer Register high byte.
pub const CANTIMH: *mut u8 = 0xE7 as *mut u8;
/// TTC Timer Register low byte.
pub const CANTTCL: *mut u8 = 0xE8 as *mut u8;
/// TTC Timer Register.
pub const CANTTC: *mut u16 = 0xE8 as *mut u16;
/// TTC Timer Register high byte.
pub const CANTTCH: *mut u8 = 0xE9 as *mut u8;
/// Transmit Error Counter Register.
pub const CANTEC: *mut u8 = 0xEA as *mut u8;
/// Receive Error Counter Register.
pub const CANREC: *mut u8 = 0xEB as *mut u8;
/// Highest Priority MOb Register.
pub const CANHPMOB: *mut u8 = 0xEC as *mut u8;
/// Page MOb Register.
pub const CANPAGE: *mut u8 = 0xED as *mut u8;
/// MOb Status Register.
pub const CANSTMOB: *mut u8 = 0xEE as *mut u8;
/// MOb Control and DLC Register.
pub const CANCDMOB: *mut u8 = 0xEF as *mut u8;
/// Identifier Tag Register 4.
pub const CANIDT4: *mut u8 = 0xF0 as *mut u8;
/// Identifier Tag Register 3.
pub const CANIDT3: *mut u8 = 0xF1 as *mut u8;
/// Identifier Tag Register 2.
pub const CANIDT2: *mut u8 = 0xF2 as *mut u8;
/// Identifier Tag Register 1.
pub const CANIDT1: *mut u8 = 0xF3 as *mut u8;
/// Identifier Mask Register 4.
pub const CANIDM4: *mut u8 = 0xF4 as *mut u8;
/// Identifier Mask Register 3.
pub const CANIDM3: *mut u8 = 0xF5 as *mut u8;
/// Identifier Mask Register 2.
pub const CANIDM2: *mut u8 = 0xF6 as *mut u8;
/// Identifier Mask Register 1.
pub const CANIDM1: *mut u8 = 0xF7 as *mut u8;
/// Time Stamp Register.
pub const CANSTM: *mut u16 = 0xF8 as *mut u16;
/// Time Stamp Register low byte.
pub const CANSTML: *mut u8 = 0xF8 as *mut u8;
/// Time Stamp Register high byte.
pub const CANSTMH: *mut u8 = 0xF9 as *mut u8;
/// Message Data Register.
pub const CANMSG: *mut u8 = 0xFA as *mut u8;