#[repr(C)]
pub struct RegisterBlock {
Show 29 fields pub afec_cr: Reg<AFEC_CR_SPEC>, pub afec_mr: Reg<AFEC_MR_SPEC>, pub afec_emr: Reg<AFEC_EMR_SPEC>, pub afec_seq1r: Reg<AFEC_SEQ1R_SPEC>, pub afec_seq2r: Reg<AFEC_SEQ2R_SPEC>, pub afec_cher: Reg<AFEC_CHER_SPEC>, pub afec_chdr: Reg<AFEC_CHDR_SPEC>, pub afec_chsr: Reg<AFEC_CHSR_SPEC>, pub afec_lcdr: Reg<AFEC_LCDR_SPEC>, pub afec_ier: Reg<AFEC_IER_SPEC>, pub afec_idr: Reg<AFEC_IDR_SPEC>, pub afec_imr: Reg<AFEC_IMR_SPEC>, pub afec_isr: Reg<AFEC_ISR_SPEC>, pub afec_over: Reg<AFEC_OVER_SPEC>, pub afec_cwr: Reg<AFEC_CWR_SPEC>, pub afec_cgr: Reg<AFEC_CGR_SPEC>, pub afec_diffr: Reg<AFEC_DIFFR_SPEC>, pub afec_cselr: Reg<AFEC_CSELR_SPEC>, pub afec_cdr: Reg<AFEC_CDR_SPEC>, pub afec_cocr: Reg<AFEC_COCR_SPEC>, pub afec_tempmr: Reg<AFEC_TEMPMR_SPEC>, pub afec_tempcwr: Reg<AFEC_TEMPCWR_SPEC>, pub afec_acr: Reg<AFEC_ACR_SPEC>, pub afec_shmr: Reg<AFEC_SHMR_SPEC>, pub afec_cosr: Reg<AFEC_COSR_SPEC>, pub afec_cvr: Reg<AFEC_CVR_SPEC>, pub afec_cecr: Reg<AFEC_CECR_SPEC>, pub afec_wpmr: Reg<AFEC_WPMR_SPEC>, pub afec_wpsr: Reg<AFEC_WPSR_SPEC>, /* private fields */
}
Expand description

Register block

Fields

afec_cr: Reg<AFEC_CR_SPEC>

0x00 - AFEC Control Register

afec_mr: Reg<AFEC_MR_SPEC>

0x04 - AFEC Mode Register

afec_emr: Reg<AFEC_EMR_SPEC>

0x08 - AFEC Extended Mode Register

afec_seq1r: Reg<AFEC_SEQ1R_SPEC>

0x0c - AFEC Channel Sequence 1 Register

afec_seq2r: Reg<AFEC_SEQ2R_SPEC>

0x10 - AFEC Channel Sequence 2 Register

afec_cher: Reg<AFEC_CHER_SPEC>

0x14 - AFEC Channel Enable Register

afec_chdr: Reg<AFEC_CHDR_SPEC>

0x18 - AFEC Channel Disable Register

afec_chsr: Reg<AFEC_CHSR_SPEC>

0x1c - AFEC Channel Status Register

afec_lcdr: Reg<AFEC_LCDR_SPEC>

0x20 - AFEC Last Converted Data Register

afec_ier: Reg<AFEC_IER_SPEC>

0x24 - AFEC Interrupt Enable Register

afec_idr: Reg<AFEC_IDR_SPEC>

0x28 - AFEC Interrupt Disable Register

afec_imr: Reg<AFEC_IMR_SPEC>

0x2c - AFEC Interrupt Mask Register

afec_isr: Reg<AFEC_ISR_SPEC>

0x30 - AFEC Interrupt Status Register

afec_over: Reg<AFEC_OVER_SPEC>

0x4c - AFEC Overrun Status Register

afec_cwr: Reg<AFEC_CWR_SPEC>

0x50 - AFEC Compare Window Register

afec_cgr: Reg<AFEC_CGR_SPEC>

0x54 - AFEC Channel Gain Register

afec_diffr: Reg<AFEC_DIFFR_SPEC>

0x60 - AFEC Channel Differential Register

afec_cselr: Reg<AFEC_CSELR_SPEC>

0x64 - AFEC Channel Selection Register

afec_cdr: Reg<AFEC_CDR_SPEC>

0x68 - AFEC Channel Data Register

afec_cocr: Reg<AFEC_COCR_SPEC>

0x6c - AFEC Channel Offset Compensation Register

afec_tempmr: Reg<AFEC_TEMPMR_SPEC>

0x70 - AFEC Temperature Sensor Mode Register

afec_tempcwr: Reg<AFEC_TEMPCWR_SPEC>

0x74 - AFEC Temperature Compare Window Register

afec_acr: Reg<AFEC_ACR_SPEC>

0x94 - AFEC Analog Control Register

afec_shmr: Reg<AFEC_SHMR_SPEC>

0xa0 - AFEC Sample & Hold Mode Register

afec_cosr: Reg<AFEC_COSR_SPEC>

0xd0 - AFEC Correction Select Register

afec_cvr: Reg<AFEC_CVR_SPEC>

0xd4 - AFEC Correction Values Register

afec_cecr: Reg<AFEC_CECR_SPEC>

0xd8 - AFEC Channel Error Correction Register

afec_wpmr: Reg<AFEC_WPMR_SPEC>

0xe4 - AFEC Write Protection Mode Register

afec_wpsr: Reg<AFEC_WPSR_SPEC>

0xe8 - AFEC Write Protection Status Register

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