atsaml21e16b/rtc/mode2/
ctrla.rs

1#[doc = "Register `CTRLA` reader"]
2pub struct R(crate::R<CTRLA_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<CTRLA_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<CTRLA_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<CTRLA_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `CTRLA` writer"]
17pub struct W(crate::W<CTRLA_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<CTRLA_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<CTRLA_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<CTRLA_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SWRST` writer - Software Reset"]
38pub type SWRST_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>;
39#[doc = "Field `ENABLE` reader - Enable"]
40pub type ENABLE_R = crate::BitReader<bool>;
41#[doc = "Field `ENABLE` writer - Enable"]
42pub type ENABLE_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>;
43#[doc = "Field `MODE` reader - Operating Mode"]
44pub type MODE_R = crate::FieldReader<u8, MODESELECT_A>;
45#[doc = "Operating Mode\n\nValue on reset: 0"]
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47#[repr(u8)]
48pub enum MODESELECT_A {
49    #[doc = "0: Mode 0: 32-bit Counter"]
50    COUNT32 = 0,
51    #[doc = "1: Mode 1: 16-bit Counter"]
52    COUNT16 = 1,
53    #[doc = "2: Mode 2: Clock/Calendar"]
54    CLOCK = 2,
55}
56impl From<MODESELECT_A> for u8 {
57    #[inline(always)]
58    fn from(variant: MODESELECT_A) -> Self {
59        variant as _
60    }
61}
62impl MODE_R {
63    #[doc = "Get enumerated values variant"]
64    #[inline(always)]
65    pub fn variant(&self) -> Option<MODESELECT_A> {
66        match self.bits {
67            0 => Some(MODESELECT_A::COUNT32),
68            1 => Some(MODESELECT_A::COUNT16),
69            2 => Some(MODESELECT_A::CLOCK),
70            _ => None,
71        }
72    }
73    #[doc = "Checks if the value of the field is `COUNT32`"]
74    #[inline(always)]
75    pub fn is_count32(&self) -> bool {
76        *self == MODESELECT_A::COUNT32
77    }
78    #[doc = "Checks if the value of the field is `COUNT16`"]
79    #[inline(always)]
80    pub fn is_count16(&self) -> bool {
81        *self == MODESELECT_A::COUNT16
82    }
83    #[doc = "Checks if the value of the field is `CLOCK`"]
84    #[inline(always)]
85    pub fn is_clock(&self) -> bool {
86        *self == MODESELECT_A::CLOCK
87    }
88}
89#[doc = "Field `MODE` writer - Operating Mode"]
90pub type MODE_W<'a, const O: u8> = crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, MODESELECT_A, 2, O>;
91impl<'a, const O: u8> MODE_W<'a, O> {
92    #[doc = "Mode 0: 32-bit Counter"]
93    #[inline(always)]
94    pub fn count32(self) -> &'a mut W {
95        self.variant(MODESELECT_A::COUNT32)
96    }
97    #[doc = "Mode 1: 16-bit Counter"]
98    #[inline(always)]
99    pub fn count16(self) -> &'a mut W {
100        self.variant(MODESELECT_A::COUNT16)
101    }
102    #[doc = "Mode 2: Clock/Calendar"]
103    #[inline(always)]
104    pub fn clock(self) -> &'a mut W {
105        self.variant(MODESELECT_A::CLOCK)
106    }
107}
108#[doc = "Field `CLKREP` reader - Clock Representation"]
109pub type CLKREP_R = crate::BitReader<bool>;
110#[doc = "Field `CLKREP` writer - Clock Representation"]
111pub type CLKREP_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>;
112#[doc = "Field `MATCHCLR` reader - Clear on Match"]
113pub type MATCHCLR_R = crate::BitReader<bool>;
114#[doc = "Field `MATCHCLR` writer - Clear on Match"]
115pub type MATCHCLR_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>;
116#[doc = "Field `PRESCALER` reader - Prescaler"]
117pub type PRESCALER_R = crate::FieldReader<u8, PRESCALERSELECT_A>;
118#[doc = "Prescaler\n\nValue on reset: 0"]
119#[derive(Clone, Copy, Debug, PartialEq, Eq)]
120#[repr(u8)]
121pub enum PRESCALERSELECT_A {
122    #[doc = "0: CLK_RTC_CNT = GCLK_RTC/1"]
123    OFF = 0,
124    #[doc = "1: CLK_RTC_CNT = GCLK_RTC/1"]
125    DIV1 = 1,
126    #[doc = "2: CLK_RTC_CNT = GCLK_RTC/2"]
127    DIV2 = 2,
128    #[doc = "3: CLK_RTC_CNT = GCLK_RTC/4"]
129    DIV4 = 3,
130    #[doc = "4: CLK_RTC_CNT = GCLK_RTC/8"]
131    DIV8 = 4,
132    #[doc = "5: CLK_RTC_CNT = GCLK_RTC/16"]
133    DIV16 = 5,
134    #[doc = "6: CLK_RTC_CNT = GCLK_RTC/32"]
135    DIV32 = 6,
136    #[doc = "7: CLK_RTC_CNT = GCLK_RTC/64"]
137    DIV64 = 7,
138    #[doc = "8: CLK_RTC_CNT = GCLK_RTC/128"]
139    DIV128 = 8,
140    #[doc = "9: CLK_RTC_CNT = GCLK_RTC/256"]
141    DIV256 = 9,
142    #[doc = "10: CLK_RTC_CNT = GCLK_RTC/512"]
143    DIV512 = 10,
144    #[doc = "11: CLK_RTC_CNT = GCLK_RTC/1024"]
145    DIV1024 = 11,
146}
147impl From<PRESCALERSELECT_A> for u8 {
148    #[inline(always)]
149    fn from(variant: PRESCALERSELECT_A) -> Self {
150        variant as _
151    }
152}
153impl PRESCALER_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> Option<PRESCALERSELECT_A> {
157        match self.bits {
158            0 => Some(PRESCALERSELECT_A::OFF),
159            1 => Some(PRESCALERSELECT_A::DIV1),
160            2 => Some(PRESCALERSELECT_A::DIV2),
161            3 => Some(PRESCALERSELECT_A::DIV4),
162            4 => Some(PRESCALERSELECT_A::DIV8),
163            5 => Some(PRESCALERSELECT_A::DIV16),
164            6 => Some(PRESCALERSELECT_A::DIV32),
165            7 => Some(PRESCALERSELECT_A::DIV64),
166            8 => Some(PRESCALERSELECT_A::DIV128),
167            9 => Some(PRESCALERSELECT_A::DIV256),
168            10 => Some(PRESCALERSELECT_A::DIV512),
169            11 => Some(PRESCALERSELECT_A::DIV1024),
170            _ => None,
171        }
172    }
173    #[doc = "Checks if the value of the field is `OFF`"]
174    #[inline(always)]
175    pub fn is_off(&self) -> bool {
176        *self == PRESCALERSELECT_A::OFF
177    }
178    #[doc = "Checks if the value of the field is `DIV1`"]
179    #[inline(always)]
180    pub fn is_div1(&self) -> bool {
181        *self == PRESCALERSELECT_A::DIV1
182    }
183    #[doc = "Checks if the value of the field is `DIV2`"]
184    #[inline(always)]
185    pub fn is_div2(&self) -> bool {
186        *self == PRESCALERSELECT_A::DIV2
187    }
188    #[doc = "Checks if the value of the field is `DIV4`"]
189    #[inline(always)]
190    pub fn is_div4(&self) -> bool {
191        *self == PRESCALERSELECT_A::DIV4
192    }
193    #[doc = "Checks if the value of the field is `DIV8`"]
194    #[inline(always)]
195    pub fn is_div8(&self) -> bool {
196        *self == PRESCALERSELECT_A::DIV8
197    }
198    #[doc = "Checks if the value of the field is `DIV16`"]
199    #[inline(always)]
200    pub fn is_div16(&self) -> bool {
201        *self == PRESCALERSELECT_A::DIV16
202    }
203    #[doc = "Checks if the value of the field is `DIV32`"]
204    #[inline(always)]
205    pub fn is_div32(&self) -> bool {
206        *self == PRESCALERSELECT_A::DIV32
207    }
208    #[doc = "Checks if the value of the field is `DIV64`"]
209    #[inline(always)]
210    pub fn is_div64(&self) -> bool {
211        *self == PRESCALERSELECT_A::DIV64
212    }
213    #[doc = "Checks if the value of the field is `DIV128`"]
214    #[inline(always)]
215    pub fn is_div128(&self) -> bool {
216        *self == PRESCALERSELECT_A::DIV128
217    }
218    #[doc = "Checks if the value of the field is `DIV256`"]
219    #[inline(always)]
220    pub fn is_div256(&self) -> bool {
221        *self == PRESCALERSELECT_A::DIV256
222    }
223    #[doc = "Checks if the value of the field is `DIV512`"]
224    #[inline(always)]
225    pub fn is_div512(&self) -> bool {
226        *self == PRESCALERSELECT_A::DIV512
227    }
228    #[doc = "Checks if the value of the field is `DIV1024`"]
229    #[inline(always)]
230    pub fn is_div1024(&self) -> bool {
231        *self == PRESCALERSELECT_A::DIV1024
232    }
233}
234#[doc = "Field `PRESCALER` writer - Prescaler"]
235pub type PRESCALER_W<'a, const O: u8> =
236    crate::FieldWriter<'a, u16, CTRLA_SPEC, u8, PRESCALERSELECT_A, 4, O>;
237impl<'a, const O: u8> PRESCALER_W<'a, O> {
238    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
239    #[inline(always)]
240    pub fn off(self) -> &'a mut W {
241        self.variant(PRESCALERSELECT_A::OFF)
242    }
243    #[doc = "CLK_RTC_CNT = GCLK_RTC/1"]
244    #[inline(always)]
245    pub fn div1(self) -> &'a mut W {
246        self.variant(PRESCALERSELECT_A::DIV1)
247    }
248    #[doc = "CLK_RTC_CNT = GCLK_RTC/2"]
249    #[inline(always)]
250    pub fn div2(self) -> &'a mut W {
251        self.variant(PRESCALERSELECT_A::DIV2)
252    }
253    #[doc = "CLK_RTC_CNT = GCLK_RTC/4"]
254    #[inline(always)]
255    pub fn div4(self) -> &'a mut W {
256        self.variant(PRESCALERSELECT_A::DIV4)
257    }
258    #[doc = "CLK_RTC_CNT = GCLK_RTC/8"]
259    #[inline(always)]
260    pub fn div8(self) -> &'a mut W {
261        self.variant(PRESCALERSELECT_A::DIV8)
262    }
263    #[doc = "CLK_RTC_CNT = GCLK_RTC/16"]
264    #[inline(always)]
265    pub fn div16(self) -> &'a mut W {
266        self.variant(PRESCALERSELECT_A::DIV16)
267    }
268    #[doc = "CLK_RTC_CNT = GCLK_RTC/32"]
269    #[inline(always)]
270    pub fn div32(self) -> &'a mut W {
271        self.variant(PRESCALERSELECT_A::DIV32)
272    }
273    #[doc = "CLK_RTC_CNT = GCLK_RTC/64"]
274    #[inline(always)]
275    pub fn div64(self) -> &'a mut W {
276        self.variant(PRESCALERSELECT_A::DIV64)
277    }
278    #[doc = "CLK_RTC_CNT = GCLK_RTC/128"]
279    #[inline(always)]
280    pub fn div128(self) -> &'a mut W {
281        self.variant(PRESCALERSELECT_A::DIV128)
282    }
283    #[doc = "CLK_RTC_CNT = GCLK_RTC/256"]
284    #[inline(always)]
285    pub fn div256(self) -> &'a mut W {
286        self.variant(PRESCALERSELECT_A::DIV256)
287    }
288    #[doc = "CLK_RTC_CNT = GCLK_RTC/512"]
289    #[inline(always)]
290    pub fn div512(self) -> &'a mut W {
291        self.variant(PRESCALERSELECT_A::DIV512)
292    }
293    #[doc = "CLK_RTC_CNT = GCLK_RTC/1024"]
294    #[inline(always)]
295    pub fn div1024(self) -> &'a mut W {
296        self.variant(PRESCALERSELECT_A::DIV1024)
297    }
298}
299#[doc = "Field `CLOCKSYNC` reader - Clock Read Synchronization Enable"]
300pub type CLOCKSYNC_R = crate::BitReader<bool>;
301#[doc = "Field `CLOCKSYNC` writer - Clock Read Synchronization Enable"]
302pub type CLOCKSYNC_W<'a, const O: u8> = crate::BitWriter<'a, u16, CTRLA_SPEC, bool, O>;
303impl R {
304    #[doc = "Bit 1 - Enable"]
305    #[inline(always)]
306    pub fn enable(&self) -> ENABLE_R {
307        ENABLE_R::new(((self.bits >> 1) & 1) != 0)
308    }
309    #[doc = "Bits 2:3 - Operating Mode"]
310    #[inline(always)]
311    pub fn mode(&self) -> MODE_R {
312        MODE_R::new(((self.bits >> 2) & 3) as u8)
313    }
314    #[doc = "Bit 6 - Clock Representation"]
315    #[inline(always)]
316    pub fn clkrep(&self) -> CLKREP_R {
317        CLKREP_R::new(((self.bits >> 6) & 1) != 0)
318    }
319    #[doc = "Bit 7 - Clear on Match"]
320    #[inline(always)]
321    pub fn matchclr(&self) -> MATCHCLR_R {
322        MATCHCLR_R::new(((self.bits >> 7) & 1) != 0)
323    }
324    #[doc = "Bits 8:11 - Prescaler"]
325    #[inline(always)]
326    pub fn prescaler(&self) -> PRESCALER_R {
327        PRESCALER_R::new(((self.bits >> 8) & 0x0f) as u8)
328    }
329    #[doc = "Bit 15 - Clock Read Synchronization Enable"]
330    #[inline(always)]
331    pub fn clocksync(&self) -> CLOCKSYNC_R {
332        CLOCKSYNC_R::new(((self.bits >> 15) & 1) != 0)
333    }
334}
335impl W {
336    #[doc = "Bit 0 - Software Reset"]
337    #[inline(always)]
338    #[must_use]
339    pub fn swrst(&mut self) -> SWRST_W<0> {
340        SWRST_W::new(self)
341    }
342    #[doc = "Bit 1 - Enable"]
343    #[inline(always)]
344    #[must_use]
345    pub fn enable(&mut self) -> ENABLE_W<1> {
346        ENABLE_W::new(self)
347    }
348    #[doc = "Bits 2:3 - Operating Mode"]
349    #[inline(always)]
350    #[must_use]
351    pub fn mode(&mut self) -> MODE_W<2> {
352        MODE_W::new(self)
353    }
354    #[doc = "Bit 6 - Clock Representation"]
355    #[inline(always)]
356    #[must_use]
357    pub fn clkrep(&mut self) -> CLKREP_W<6> {
358        CLKREP_W::new(self)
359    }
360    #[doc = "Bit 7 - Clear on Match"]
361    #[inline(always)]
362    #[must_use]
363    pub fn matchclr(&mut self) -> MATCHCLR_W<7> {
364        MATCHCLR_W::new(self)
365    }
366    #[doc = "Bits 8:11 - Prescaler"]
367    #[inline(always)]
368    #[must_use]
369    pub fn prescaler(&mut self) -> PRESCALER_W<8> {
370        PRESCALER_W::new(self)
371    }
372    #[doc = "Bit 15 - Clock Read Synchronization Enable"]
373    #[inline(always)]
374    #[must_use]
375    pub fn clocksync(&mut self) -> CLOCKSYNC_W<15> {
376        CLOCKSYNC_W::new(self)
377    }
378    #[doc = "Writes raw bits to the register."]
379    #[inline(always)]
380    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
381        self.0.bits(bits);
382        self
383    }
384}
385#[doc = "MODE2 Control A\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrla](index.html) module"]
386pub struct CTRLA_SPEC;
387impl crate::RegisterSpec for CTRLA_SPEC {
388    type Ux = u16;
389}
390#[doc = "`read()` method returns [ctrla::R](R) reader structure"]
391impl crate::Readable for CTRLA_SPEC {
392    type Reader = R;
393}
394#[doc = "`write(|w| ..)` method takes [ctrla::W](W) writer structure"]
395impl crate::Writable for CTRLA_SPEC {
396    type Writer = W;
397    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
398    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
399}
400#[doc = "`reset()` method sets CTRLA to value 0"]
401impl crate::Resettable for CTRLA_SPEC {
402    const RESET_VALUE: Self::Ux = 0;
403}
atsaml21e16b/rtc/mode2/ctrla.rs

atsaml21e16b/rtc/mode2/
ctrla.rs
