[−][src]Type Definition atsame70q20b::twihs0::twihs_idr::W
type W = W<u32, TWIHS_IDR>;
Writer for register TWIHS_IDR
Implementations
impl W
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pub fn txcomp(&mut self) -> TXCOMP_W
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Bit 0 - Transmission Completed Interrupt Disable
pub fn rxrdy(&mut self) -> RXRDY_W
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Bit 1 - Receive Holding Register Ready Interrupt Disable
pub fn txrdy(&mut self) -> TXRDY_W
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Bit 2 - Transmit Holding Register Ready Interrupt Disable
pub fn svacc(&mut self) -> SVACC_W
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Bit 4 - Slave Access Interrupt Disable
pub fn gacc(&mut self) -> GACC_W
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Bit 5 - General Call Access Interrupt Disable
pub fn ovre(&mut self) -> OVRE_W
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Bit 6 - Overrun Error Interrupt Disable
pub fn unre(&mut self) -> UNRE_W
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Bit 7 - Underrun Error Interrupt Disable
pub fn nack(&mut self) -> NACK_W
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Bit 8 - Not Acknowledge Interrupt Disable
pub fn arblst(&mut self) -> ARBLST_W
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Bit 9 - Arbitration Lost Interrupt Disable
pub fn scl_ws(&mut self) -> SCL_WS_W
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Bit 10 - Clock Wait State Interrupt Disable
pub fn eosacc(&mut self) -> EOSACC_W
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Bit 11 - End Of Slave Access Interrupt Disable
pub fn mcack(&mut self) -> MCACK_W
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Bit 16 - Master Code Acknowledge Interrupt Disable
pub fn tout(&mut self) -> TOUT_W
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Bit 18 - Timeout Error Interrupt Disable
pub fn pecerr(&mut self) -> PECERR_W
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Bit 19 - PEC Error Interrupt Disable
pub fn smbdam(&mut self) -> SMBDAM_W
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Bit 20 - SMBus Default Address Match Interrupt Disable
pub fn smbhhm(&mut self) -> SMBHHM_W
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Bit 21 - SMBus Host Header Address Match Interrupt Disable