Type Definition atsame70n20b_pac::usbhs::devidr::W[−][src]

type W = W<u32, DEVIDR>;

Writer for register DEVIDR

Implementations

impl W[src]

pub fn suspec(&mut self) -> SUSPEC_W<'_>[src]

Bit 0 - Suspend Interrupt Disable

pub fn msofec(&mut self) -> MSOFEC_W<'_>[src]

Bit 1 - Micro Start of Frame Interrupt Disable

pub fn sofec(&mut self) -> SOFEC_W<'_>[src]

Bit 2 - Start of Frame Interrupt Disable

pub fn eorstec(&mut self) -> EORSTEC_W<'_>[src]

Bit 3 - End of Reset Interrupt Disable

pub fn wakeupec(&mut self) -> WAKEUPEC_W<'_>[src]

Bit 4 - Wake-Up Interrupt Disable

pub fn eorsmec(&mut self) -> EORSMEC_W<'_>[src]

Bit 5 - End of Resume Interrupt Disable

pub fn uprsmec(&mut self) -> UPRSMEC_W<'_>[src]

Bit 6 - Upstream Resume Interrupt Disable

pub fn pep_0(&mut self) -> PEP_0_W<'_>[src]

Bit 12 - Endpoint 0 Interrupt Disable

pub fn pep_1(&mut self) -> PEP_1_W<'_>[src]

Bit 13 - Endpoint 1 Interrupt Disable

pub fn pep_2(&mut self) -> PEP_2_W<'_>[src]

Bit 14 - Endpoint 2 Interrupt Disable

pub fn pep_3(&mut self) -> PEP_3_W<'_>[src]

Bit 15 - Endpoint 3 Interrupt Disable

pub fn pep_4(&mut self) -> PEP_4_W<'_>[src]

Bit 16 - Endpoint 4 Interrupt Disable

pub fn pep_5(&mut self) -> PEP_5_W<'_>[src]

Bit 17 - Endpoint 5 Interrupt Disable

pub fn pep_6(&mut self) -> PEP_6_W<'_>[src]

Bit 18 - Endpoint 6 Interrupt Disable

pub fn pep_7(&mut self) -> PEP_7_W<'_>[src]

Bit 19 - Endpoint 7 Interrupt Disable

pub fn pep_8(&mut self) -> PEP_8_W<'_>[src]

Bit 20 - Endpoint 8 Interrupt Disable

pub fn pep_9(&mut self) -> PEP_9_W<'_>[src]

Bit 21 - Endpoint 9 Interrupt Disable

pub fn dma_1(&mut self) -> DMA_1_W<'_>[src]

Bit 25 - DMA Channel 1 Interrupt Disable

pub fn dma_2(&mut self) -> DMA_2_W<'_>[src]

Bit 26 - DMA Channel 2 Interrupt Disable

pub fn dma_3(&mut self) -> DMA_3_W<'_>[src]

Bit 27 - DMA Channel 3 Interrupt Disable

pub fn dma_4(&mut self) -> DMA_4_W<'_>[src]

Bit 28 - DMA Channel 4 Interrupt Disable

pub fn dma_5(&mut self) -> DMA_5_W<'_>[src]

Bit 29 - DMA Channel 5 Interrupt Disable

pub fn dma_6(&mut self) -> DMA_6_W<'_>[src]

Bit 30 - DMA Channel 6 Interrupt Disable

pub fn dma_7(&mut self) -> DMA_7_W<'_>[src]

Bit 31 - DMA Channel 7 Interrupt Disable