Struct atsame70n19_pac::pwm0::RegisterBlock [−][src]
#[repr(C)]pub struct RegisterBlock {Show 45 fields
pub clk: Reg<CLK_SPEC>,
pub ena: Reg<ENA_SPEC>,
pub dis: Reg<DIS_SPEC>,
pub sr: Reg<SR_SPEC>,
pub ier1: Reg<IER1_SPEC>,
pub idr1: Reg<IDR1_SPEC>,
pub imr1: Reg<IMR1_SPEC>,
pub isr1: Reg<ISR1_SPEC>,
pub scm: Reg<SCM_SPEC>,
pub dmar: Reg<DMAR_SPEC>,
pub scuc: Reg<SCUC_SPEC>,
pub scup: Reg<SCUP_SPEC>,
pub scupupd: Reg<SCUPUPD_SPEC>,
pub ier2: Reg<IER2_SPEC>,
pub idr2: Reg<IDR2_SPEC>,
pub imr2: Reg<IMR2_SPEC>,
pub isr2: Reg<ISR2_SPEC>,
pub oov: Reg<OOV_SPEC>,
pub os: Reg<OS_SPEC>,
pub oss: Reg<OSS_SPEC>,
pub osc: Reg<OSC_SPEC>,
pub ossupd: Reg<OSSUPD_SPEC>,
pub oscupd: Reg<OSCUPD_SPEC>,
pub fmr: Reg<FMR_SPEC>,
pub fsr: Reg<FSR_SPEC>,
pub fcr: Reg<FCR_SPEC>,
pub fpv1: Reg<FPV1_SPEC>,
pub fpe: Reg<FPE_SPEC>,
pub elmr: [Reg<ELMR_SPEC>; 2],
pub sspr: Reg<SSPR_SPEC>,
pub sspup: Reg<SSPUP_SPEC>,
pub smmr: Reg<SMMR_SPEC>,
pub fpv2: Reg<FPV2_SPEC>,
pub wpcr: Reg<WPCR_SPEC>,
pub wpsr: Reg<WPSR_SPEC>,
pub pwm_cmp: [PWM_CMP; 8],
pub pwm_ch_num: [PWM_CH_NUM; 4],
pub cmupd0: Reg<CMUPD0_SPEC>,
pub cmupd1: Reg<CMUPD1_SPEC>,
pub etrg1: Reg<ETRG1_SPEC>,
pub lebr1: Reg<LEBR1_SPEC>,
pub cmupd2: Reg<CMUPD2_SPEC>,
pub etrg2: Reg<ETRG2_SPEC>,
pub lebr2: Reg<LEBR2_SPEC>,
pub cmupd3: Reg<CMUPD3_SPEC>,
// some fields omitted
}
Expand description
Register block
Fields
clk: Reg<CLK_SPEC>
0x00 - PWM Clock Register
ena: Reg<ENA_SPEC>
0x04 - PWM Enable Register
dis: Reg<DIS_SPEC>
0x08 - PWM Disable Register
sr: Reg<SR_SPEC>
0x0c - PWM Status Register
ier1: Reg<IER1_SPEC>
0x10 - PWM Interrupt Enable Register 1
idr1: Reg<IDR1_SPEC>
0x14 - PWM Interrupt Disable Register 1
imr1: Reg<IMR1_SPEC>
0x18 - PWM Interrupt Mask Register 1
isr1: Reg<ISR1_SPEC>
0x1c - PWM Interrupt Status Register 1
scm: Reg<SCM_SPEC>
0x20 - PWM Sync Channels Mode Register
dmar: Reg<DMAR_SPEC>
0x24 - PWM DMA Register
scuc: Reg<SCUC_SPEC>
0x28 - PWM Sync Channels Update Control Register
scup: Reg<SCUP_SPEC>
0x2c - PWM Sync Channels Update Period Register
scupupd: Reg<SCUPUPD_SPEC>
0x30 - PWM Sync Channels Update Period Update Register
ier2: Reg<IER2_SPEC>
0x34 - PWM Interrupt Enable Register 2
idr2: Reg<IDR2_SPEC>
0x38 - PWM Interrupt Disable Register 2
imr2: Reg<IMR2_SPEC>
0x3c - PWM Interrupt Mask Register 2
isr2: Reg<ISR2_SPEC>
0x40 - PWM Interrupt Status Register 2
oov: Reg<OOV_SPEC>
0x44 - PWM Output Override Value Register
os: Reg<OS_SPEC>
0x48 - PWM Output Selection Register
oss: Reg<OSS_SPEC>
0x4c - PWM Output Selection Set Register
osc: Reg<OSC_SPEC>
0x50 - PWM Output Selection Clear Register
ossupd: Reg<OSSUPD_SPEC>
0x54 - PWM Output Selection Set Update Register
oscupd: Reg<OSCUPD_SPEC>
0x58 - PWM Output Selection Clear Update Register
fmr: Reg<FMR_SPEC>
0x5c - PWM Fault Mode Register
fsr: Reg<FSR_SPEC>
0x60 - PWM Fault Status Register
fcr: Reg<FCR_SPEC>
0x64 - PWM Fault Clear Register
fpv1: Reg<FPV1_SPEC>
0x68 - PWM Fault Protection Value Register 1
fpe: Reg<FPE_SPEC>
0x6c - PWM Fault Protection Enable Register
elmr: [Reg<ELMR_SPEC>; 2]
0x7c..0x84 - PWM Event Line 0 Mode Register 0
sspr: Reg<SSPR_SPEC>
0xa0 - PWM Spread Spectrum Register
sspup: Reg<SSPUP_SPEC>
0xa4 - PWM Spread Spectrum Update Register
smmr: Reg<SMMR_SPEC>
0xb0 - PWM Stepper Motor Mode Register
fpv2: Reg<FPV2_SPEC>
0xc0 - PWM Fault Protection Value 2 Register
wpcr: Reg<WPCR_SPEC>
0xe4 - PWM Write Protection Control Register
wpsr: Reg<WPSR_SPEC>
0xe8 - PWM Write Protection Status Register
pwm_cmp: [PWM_CMP; 8]
0x130..0x1b0 - PWM Comparison 0 Value Register
pwm_ch_num: [PWM_CH_NUM; 4]
0x200..0x280 - PWM Channel Mode Register (ch_num = 0)
cmupd0: Reg<CMUPD0_SPEC>
0x400 - PWM Channel Mode Update Register (ch_num = 0)
cmupd1: Reg<CMUPD1_SPEC>
0x420 - PWM Channel Mode Update Register (ch_num = 1)
etrg1: Reg<ETRG1_SPEC>
0x42c - PWM External Trigger Register (trg_num = 1)
lebr1: Reg<LEBR1_SPEC>
0x430 - PWM Leading-Edge Blanking Register (trg_num = 1)
cmupd2: Reg<CMUPD2_SPEC>
0x440 - PWM Channel Mode Update Register (ch_num = 2)
etrg2: Reg<ETRG2_SPEC>
0x44c - PWM External Trigger Register (trg_num = 2)
lebr2: Reg<LEBR2_SPEC>
0x450 - PWM Leading-Edge Blanking Register (trg_num = 2)
cmupd3: Reg<CMUPD3_SPEC>
0x460 - PWM Channel Mode Update Register (ch_num = 3)