[−][src]Type Definition atsame70j21b::gmac::gmac_dcfgr::W
type W = W<u32, GMAC_DCFGR>;
Writer for register GMAC_DCFGR
Implementations
impl W
[src]
pub fn fbldo(&mut self) -> FBLDO_W
[src]
Bits 0:4 - Fixed Burst Length for DMA Data Operations:
pub fn esma(&mut self) -> ESMA_W
[src]
Bit 6 - Endian Swap Mode Enable for Management Descriptor Accesses
pub fn espa(&mut self) -> ESPA_W
[src]
Bit 7 - Endian Swap Mode Enable for Packet Data Accesses
pub fn rxbms(&mut self) -> RXBMS_W
[src]
Bits 8:9 - Receiver Packet Buffer Memory Size Select
pub fn txpbms(&mut self) -> TXPBMS_W
[src]
Bit 10 - Transmitter Packet Buffer Memory Size Select
pub fn txcoen(&mut self) -> TXCOEN_W
[src]
Bit 11 - Transmitter Checksum Generation Offload Enable
pub fn drbs(&mut self) -> DRBS_W
[src]
Bits 16:23 - DMA Receive Buffer Size
pub fn ddrp(&mut self) -> DDRP_W
[src]
Bit 24 - DMA Discard Receive Packets