pub type W = W<CTRLB_SPEC>;
Expand description
Register CTRLB
writer
Aliased Type§
struct W { /* private fields */ }
Implementations§
source§impl W
impl W
sourcepub fn mode(&mut self) -> MODE_W<'_, CTRLB_SPEC, 0>
pub fn mode(&mut self) -> MODE_W<'_, CTRLB_SPEC, 0>
Bit 0 - Serial Memory Mode
sourcepub fn loopen(&mut self) -> LOOPEN_W<'_, CTRLB_SPEC, 1>
pub fn loopen(&mut self) -> LOOPEN_W<'_, CTRLB_SPEC, 1>
Bit 1 - Local Loopback Enable
sourcepub fn wdrbt(&mut self) -> WDRBT_W<'_, CTRLB_SPEC, 2>
pub fn wdrbt(&mut self) -> WDRBT_W<'_, CTRLB_SPEC, 2>
Bit 2 - Wait Data Read Before Transfer
sourcepub fn smemreg(&mut self) -> SMEMREG_W<'_, CTRLB_SPEC, 3>
pub fn smemreg(&mut self) -> SMEMREG_W<'_, CTRLB_SPEC, 3>
Bit 3 - Serial Memory reg
sourcepub fn csmode(&mut self) -> CSMODE_W<'_, CTRLB_SPEC, 4>
pub fn csmode(&mut self) -> CSMODE_W<'_, CTRLB_SPEC, 4>
Bits 4:5 - Chip Select Mode
sourcepub fn datalen(&mut self) -> DATALEN_W<'_, CTRLB_SPEC, 8>
pub fn datalen(&mut self) -> DATALEN_W<'_, CTRLB_SPEC, 8>
Bits 8:11 - Data Length
sourcepub fn dlybct(&mut self) -> DLYBCT_W<'_, CTRLB_SPEC, 16>
pub fn dlybct(&mut self) -> DLYBCT_W<'_, CTRLB_SPEC, 16>
Bits 16:23 - Delay Between Consecutive Transfers
sourcepub fn dlycs(&mut self) -> DLYCS_W<'_, CTRLB_SPEC, 24>
pub fn dlycs(&mut self) -> DLYCS_W<'_, CTRLB_SPEC, 24>
Bits 24:31 - Minimum Inactive CS Delay