[][src]Type Definition atsame54n::can0::ir::W

type W = W<u32, IR>;

Writer for register IR

Implementations

impl W[src]

pub fn rf0n(&mut self) -> RF0N_W<'_>[src]

Bit 0 - Rx FIFO 0 New Message

pub fn rf0w(&mut self) -> RF0W_W<'_>[src]

Bit 1 - Rx FIFO 0 Watermark Reached

pub fn rf0f(&mut self) -> RF0F_W<'_>[src]

Bit 2 - Rx FIFO 0 Full

pub fn rf0l(&mut self) -> RF0L_W<'_>[src]

Bit 3 - Rx FIFO 0 Message Lost

pub fn rf1n(&mut self) -> RF1N_W<'_>[src]

Bit 4 - Rx FIFO 1 New Message

pub fn rf1w(&mut self) -> RF1W_W<'_>[src]

Bit 5 - Rx FIFO 1 Watermark Reached

pub fn rf1f(&mut self) -> RF1F_W<'_>[src]

Bit 6 - Rx FIFO 1 FIFO Full

pub fn rf1l(&mut self) -> RF1L_W<'_>[src]

Bit 7 - Rx FIFO 1 Message Lost

pub fn hpm(&mut self) -> HPM_W<'_>[src]

Bit 8 - High Priority Message

pub fn tc(&mut self) -> TC_W<'_>[src]

Bit 9 - Timestamp Completed

pub fn tcf(&mut self) -> TCF_W<'_>[src]

Bit 10 - Transmission Cancellation Finished

pub fn tfe(&mut self) -> TFE_W<'_>[src]

Bit 11 - Tx FIFO Empty

pub fn tefn(&mut self) -> TEFN_W<'_>[src]

Bit 12 - Tx Event FIFO New Entry

pub fn tefw(&mut self) -> TEFW_W<'_>[src]

Bit 13 - Tx Event FIFO Watermark Reached

pub fn teff(&mut self) -> TEFF_W<'_>[src]

Bit 14 - Tx Event FIFO Full

pub fn tefl(&mut self) -> TEFL_W<'_>[src]

Bit 15 - Tx Event FIFO Element Lost

pub fn tsw(&mut self) -> TSW_W<'_>[src]

Bit 16 - Timestamp Wraparound

pub fn mraf(&mut self) -> MRAF_W<'_>[src]

Bit 17 - Message RAM Access Failure

pub fn too(&mut self) -> TOO_W<'_>[src]

Bit 18 - Timeout Occurred

pub fn drx(&mut self) -> DRX_W<'_>[src]

Bit 19 - Message stored to Dedicated Rx Buffer

pub fn bec(&mut self) -> BEC_W<'_>[src]

Bit 20 - Bit Error Corrected

pub fn beu(&mut self) -> BEU_W<'_>[src]

Bit 21 - Bit Error Uncorrected

pub fn elo(&mut self) -> ELO_W<'_>[src]

Bit 22 - Error Logging Overflow

pub fn ep(&mut self) -> EP_W<'_>[src]

Bit 23 - Error Passive

pub fn ew(&mut self) -> EW_W<'_>[src]

Bit 24 - Warning Status

pub fn bo(&mut self) -> BO_W<'_>[src]

Bit 25 - Bus_Off Status

pub fn wdi(&mut self) -> WDI_W<'_>[src]

Bit 26 - Watchdog Interrupt

pub fn pea(&mut self) -> PEA_W<'_>[src]

Bit 27 - Protocol Error in Arbitration Phase

pub fn ped(&mut self) -> PED_W<'_>[src]

Bit 28 - Protocol Error in Data Phase

pub fn ara(&mut self) -> ARA_W<'_>[src]

Bit 29 - Access to Reserved Address