Expand description
Control Area Network
Modules§
- CC Control
- Core Release
- Fast Bit Timing and Prescaler
- Error Counter
- Endian
- Global Filter Configuration
- High Priority Message Status
- Interrupt Enable
- Interrupt Line Enable
- Interrupt Line Select
- Interrupt
- Message RAM Configuration
- Nominal Bit Timing and Prescaler
- New Data 1
- New Data 2
- Protocol Status
- RAM Watchdog
- Rx Buffer Configuration
- Rx Buffer / FIFO Element Size Configuration
- Rx FIFO 0 Acknowledge
- Rx FIFO 0 Configuration
- Rx FIFO 0 Status
- Rx FIFO 1 Acknowledge
- Rx FIFO 1 Configuration
- Rx FIFO 1 Status
- Standard ID Filter Configuration
- Extended ID Filter Configuration
- Test
- Timeout Counter Configuration
- Timeout Counter Value
- Timestamp Counter Configuration
- Timestamp Counter Value
- Tx Buffer Add Request
- Tx Buffer Configuration
- Tx Buffer Cancellation Finished
- Tx Buffer Cancellation Finished Interrupt Enable
- Tx Buffer Cancellation Request
- Tx Buffer Request Pending
- Tx Buffer Transmission Interrupt Enable
- Tx Buffer Transmission Occurred
- Tx Event FIFO Acknowledge
- Tx Event FIFO Configuration
- Tx Event FIFO Status
- Tx Buffer Element Size Configuration
- Tx FIFO / Queue Status
- Extended ID AND Mask
- Extended ID Filter Configuration
Structs§
- Register block
Type Aliases§
- CCCR (rw) register accessor: CC Control
- CREL (r) register accessor: Core Release
- DBTP (rw) register accessor: Fast Bit Timing and Prescaler
- ECR (r) register accessor: Error Counter
- ENDN (r) register accessor: Endian
- GFC (rw) register accessor: Global Filter Configuration
- HPMS (r) register accessor: High Priority Message Status
- IE (rw) register accessor: Interrupt Enable
- ILE (rw) register accessor: Interrupt Line Enable
- ILS (rw) register accessor: Interrupt Line Select
- IR (rw) register accessor: Interrupt
- MRCFG (rw) register accessor: Message RAM Configuration
- NBTP (rw) register accessor: Nominal Bit Timing and Prescaler
- NDAT1 (rw) register accessor: New Data 1
- NDAT2 (rw) register accessor: New Data 2
- PSR (r) register accessor: Protocol Status
- RWD (rw) register accessor: RAM Watchdog
- RXBC (rw) register accessor: Rx Buffer Configuration
- RXESC (rw) register accessor: Rx Buffer / FIFO Element Size Configuration
- RXF0A (rw) register accessor: Rx FIFO 0 Acknowledge
- RXF0C (rw) register accessor: Rx FIFO 0 Configuration
- RXF0S (r) register accessor: Rx FIFO 0 Status
- RXF1A (rw) register accessor: Rx FIFO 1 Acknowledge
- RXF1C (rw) register accessor: Rx FIFO 1 Configuration
- RXF1S (r) register accessor: Rx FIFO 1 Status
- SIDFC (rw) register accessor: Standard ID Filter Configuration
- TDCR (rw) register accessor: Extended ID Filter Configuration
- TEST (rw) register accessor: Test
- TOCC (rw) register accessor: Timeout Counter Configuration
- TOCV (rw) register accessor: Timeout Counter Value
- TSCC (rw) register accessor: Timestamp Counter Configuration
- TSCV (r) register accessor: Timestamp Counter Value
- TXBAR (rw) register accessor: Tx Buffer Add Request
- TXBC (rw) register accessor: Tx Buffer Configuration
- TXBCF (r) register accessor: Tx Buffer Cancellation Finished
- TXBCIE (rw) register accessor: Tx Buffer Cancellation Finished Interrupt Enable
- TXBCR (rw) register accessor: Tx Buffer Cancellation Request
- TXBRP (r) register accessor: Tx Buffer Request Pending
- TXBTIE (rw) register accessor: Tx Buffer Transmission Interrupt Enable
- TXBTO (r) register accessor: Tx Buffer Transmission Occurred
- TXEFA (rw) register accessor: Tx Event FIFO Acknowledge
- TXEFC (rw) register accessor: Tx Event FIFO Configuration
- TXEFS (r) register accessor: Tx Event FIFO Status
- TXESC (rw) register accessor: Tx Buffer Element Size Configuration
- TXFQS (r) register accessor: Tx FIFO / Queue Status
- XIDAM (rw) register accessor: Extended ID AND Mask
- XIDFC (rw) register accessor: Extended ID Filter Configuration