Struct atsamd51j::sdhc0::RegisterBlock
source · #[repr(C)]pub struct RegisterBlock {Show 30 fields
pub bsr: BSR,
pub bcr: BCR,
pub arg1r: ARG1R,
pub tmr: TMR,
pub cr: CR,
pub rr: [RR; 4],
pub bdpr: BDPR,
pub psr: PSR,
pub pcr: PCR,
pub wcr: WCR,
pub ccr: CCR,
pub tcr: TCR,
pub srr: SRR,
pub acesr: ACESR,
pub ca0r: CA0R,
pub ca1r: CA1R,
pub mccar: MCCAR,
pub feraces: FERACES,
pub fereis: FEREIS,
pub aesr: AESR,
pub asar: [ASAR; 1],
pub pvr: [PVR; 8],
pub sisr: SISR,
pub hcvr: HCVR,
pub mc1r: MC1R,
pub mc2r: MC2R,
pub acr: ACR,
pub cc2r: CC2R,
pub cacr: CACR,
pub dbgr: DBGR,
/* private fields */
}
Expand description
Register block
Fields§
§bsr: BSR
0x04 - Block Size
bcr: BCR
0x06 - Block Count
arg1r: ARG1R
0x08 - Argument 1
tmr: TMR
0x0c - Transfer Mode
cr: CR
0x0e - Command
rr: [RR; 4]
0x10..0x20 - Response
bdpr: BDPR
0x20 - Buffer Data Port
psr: PSR
0x24 - Present State
pcr: PCR
0x29 - Power Control
wcr: WCR
0x2b - Wakeup Control
ccr: CCR
0x2c - Clock Control
tcr: TCR
0x2e - Timeout Control
srr: SRR
0x2f - Software Reset
acesr: ACESR
0x3c - Auto CMD Error Status
ca0r: CA0R
0x40 - Capabilities 0
ca1r: CA1R
0x44 - Capabilities 1
mccar: MCCAR
0x48 - Maximum Current Capabilities
feraces: FERACES
0x50 - Force Event for Auto CMD Error Status
fereis: FEREIS
0x52 - Force Event for Error Interrupt Status
aesr: AESR
0x54 - ADMA Error Status
asar: [ASAR; 1]
0x58 - ADMA System Address n
pvr: [PVR; 8]
0x60..0x70 - Preset Value n
sisr: SISR
0xfc - Slot Interrupt Status
hcvr: HCVR
0xfe - Host Controller Version
mc1r: MC1R
0x204 - MMC Control 1
mc2r: MC2R
0x205 - MMC Control 2
acr: ACR
0x208 - AHB Control
cc2r: CC2R
0x20c - Clock Control 2
cacr: CACR
0x230 - Capabilities Control
dbgr: DBGR
0x234 - Debug
Implementations§
source§impl RegisterBlock
impl RegisterBlock
sourcepub const fn ssar_cmd23_mode(&self) -> &SSAR_CMD23_MODE
pub const fn ssar_cmd23_mode(&self) -> &SSAR_CMD23_MODE
0x00 - SDMA System Address / Argument 2
sourcepub const fn hc1r_emmc_mode(&self) -> &HC1R_EMMC_MODE
pub const fn hc1r_emmc_mode(&self) -> &HC1R_EMMC_MODE
0x28 - Host Control 1
sourcepub const fn bgcr_emmc_mode(&self) -> &BGCR_EMMC_MODE
pub const fn bgcr_emmc_mode(&self) -> &BGCR_EMMC_MODE
0x2a - Block Gap Control
sourcepub const fn nistr_emmc_mode(&self) -> &NISTR_EMMC_MODE
pub const fn nistr_emmc_mode(&self) -> &NISTR_EMMC_MODE
0x30 - Normal Interrupt Status
sourcepub const fn eistr_emmc_mode(&self) -> &EISTR_EMMC_MODE
pub const fn eistr_emmc_mode(&self) -> &EISTR_EMMC_MODE
0x32 - Error Interrupt Status
sourcepub const fn nister_emmc_mode(&self) -> &NISTER_EMMC_MODE
pub const fn nister_emmc_mode(&self) -> &NISTER_EMMC_MODE
0x34 - Normal Interrupt Status Enable
sourcepub const fn eister_emmc_mode(&self) -> &EISTER_EMMC_MODE
pub const fn eister_emmc_mode(&self) -> &EISTER_EMMC_MODE
0x36 - Error Interrupt Status Enable
sourcepub const fn nisier_emmc_mode(&self) -> &NISIER_EMMC_MODE
pub const fn nisier_emmc_mode(&self) -> &NISIER_EMMC_MODE
0x38 - Normal Interrupt Signal Enable
sourcepub const fn eisier_emmc_mode(&self) -> &EISIER_EMMC_MODE
pub const fn eisier_emmc_mode(&self) -> &EISIER_EMMC_MODE
0x3a - Error Interrupt Signal Enable
sourcepub const fn hc2r_emmc_mode(&self) -> &HC2R_EMMC_MODE
pub const fn hc2r_emmc_mode(&self) -> &HC2R_EMMC_MODE
0x3e - Host Control 2