Type Definition atsamd21e18a::gclk::GENDIV

type GENDIV = Reg<u32, _GENDIV>;

Generic Clock Generator Division

This register you can read, reset, write, write_with_zero, modify. See API.

For information about available fields see gendiv module

Trait Implementations

impl Readable for GENDIV

read() method returns gendiv::R reader structure

impl ResetValue for GENDIV

Register GENDIV reset()'s with value 0

type Type = u32

Raw register type (u8, u16, u32, ...).

fn reset_value() -> Self::Type

Reset value of the register.

impl Writable for GENDIV

write(|w| ..) method takes gendiv::W writer structure